From: sashiko-bot@kernel.org
To: "Nathan Lynch via B4 Relay" <devnull+nathan.lynch.amd.com@kernel.org>
Cc: vkoul@kernel.org, Frank.Li@kernel.org, dmaengine@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v2 10/23] dmaengine: sdxi: Complete administrative context jump start
Date: Wed, 13 May 2026 03:54:30 +0000 [thread overview]
Message-ID: <20260513035431.41FEFC2BCC7@smtp.kernel.org> (raw)
In-Reply-To: <20260511-sdxi-base-v2-10-889cfed17e3f@amd.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Using a non-atomic 64-bit fallback for a hardware doorbell register causes torn writes and device state corruption on 32-bit architectures.
--
commit 1c8a47b1b7cac23ca82b3d7ffe7b54c6cf98827e
Author: Nathan Lynch <nathan.lynch@amd.com>
dmaengine: sdxi: Complete administrative context jump start
This commit completes the SDXI administrative context initialization by
writing to its doorbell once the function is placed in the active state.
It introduces a new helper function for pushing the doorbell, which will
be used across all descriptor submission paths.
> diff --git a/drivers/dma/sdxi/context.h b/drivers/dma/sdxi/context.h
> index 65b773446ba31..8dd6beb7a6424 100644
> --- a/drivers/dma/sdxi/context.h
> +++ b/drivers/dma/sdxi/context.h
> @@ -7,6 +7,7 @@
> #define DMA_SDXI_CONTEXT_H
>
> #include <linux/dma-mapping.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
Does including linux/io-64-nonatomic-lo-hi.h in a shared header risk
polluting the compilation unit? It appears this might blindly convert all
missing 64-bit I/O operations into non-atomic fallbacks for any file that
includes context.h.
> #include <linux/types.h>
>
> #include "hw.h"
[ ... ]
> @@ -58,4 +59,9 @@ struct sdxi_cxt {
>
> int sdxi_admin_cxt_init(struct sdxi_dev *sdxi);
>
> +static inline void sdxi_cxt_push_doorbell(struct sdxi_cxt *cxt, u64 index)
> +{
> + iowrite64(index, cxt->db);
On 32-bit architectures without native 64-bit I/O, the non-atomic fallback
splits this 64-bit write into two 32-bit writes (lower 32 bits, then upper
32 bits).
Since this is a doorbell register that triggers hardware actions, could a torn
write expose a transient, invalid index to the device before the upper bits
are written?
For example, if the index crosses a 32-bit boundary, the hardware might
observe a corrupted index and begin processing an invalid ring state.
Should the driver depend on CONFIG_64BIT if atomic 64-bit writes are
mandatory, or use a safe, hardware-specific 32-bit doorbell mechanism
instead?
> +}
> +
> #endif /* DMA_SDXI_CONTEXT_H */
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-sdxi-base-v2-0-889cfed17e3f@amd.com?part=10
next prev parent reply other threads:[~2026-05-13 3:54 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 19:16 [PATCH v2 00/23] dmaengine: Smart Data Accelerator Interface (SDXI) basic support Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 01/23] PCI: Add SNIA SDXI accelerator sub-class Nathan Lynch via B4 Relay
2026-05-11 20:48 ` Frank Li
2026-05-12 23:50 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 02/23] MAINTAINERS: Add entry for SDXI driver Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 03/23] dmaengine: sdxi: Add PCI initialization Nathan Lynch via B4 Relay
2026-05-11 21:22 ` Frank Li
2026-05-13 0:05 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 04/23] dmaengine: sdxi: Feature discovery and initial configuration Nathan Lynch via B4 Relay
2026-05-11 21:30 ` Frank Li
2026-05-13 0:33 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 05/23] dmaengine: sdxi: Configure context tables Nathan Lynch via B4 Relay
2026-05-13 1:12 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 06/23] dmaengine: sdxi: Allocate DMA pools Nathan Lynch via B4 Relay
2026-05-13 1:30 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 07/23] dmaengine: sdxi: Allocate administrative context Nathan Lynch via B4 Relay
2026-05-13 2:20 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 08/23] dmaengine: sdxi: Install " Nathan Lynch via B4 Relay
2026-05-13 3:17 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 09/23] dmaengine: sdxi: Start functions on probe, stop on remove Nathan Lynch via B4 Relay
2026-05-13 3:35 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 10/23] dmaengine: sdxi: Complete administrative context jump start Nathan Lynch via B4 Relay
2026-05-13 3:54 ` sashiko-bot [this message]
2026-05-11 19:16 ` [PATCH v2 11/23] dmaengine: sdxi: Add client context alloc and release APIs Nathan Lynch via B4 Relay
2026-05-13 4:46 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 12/23] dmaengine: sdxi: Add descriptor ring management Nathan Lynch via B4 Relay
2026-05-13 5:21 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 13/23] dmaengine: sdxi: Add unit tests for descriptor ring reservations Nathan Lynch via B4 Relay
2026-05-13 5:48 ` sashiko-bot
2026-05-11 19:16 ` [PATCH v2 14/23] dmaengine: sdxi: Attach descriptor ring state to contexts Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 15/23] dmaengine: sdxi: Per-context access key (AKey) table entry allocator Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 16/23] dmaengine: sdxi: Generic descriptor manipulation helpers Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 17/23] dmaengine: sdxi: Add completion status block API Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 18/23] dmaengine: sdxi: Encode context start, stop, and sync descriptors Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 19/23] dmaengine: sdxi: Provide context start and stop APIs Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 20/23] dmaengine: sdxi: Encode nop, copy, and interrupt descriptors Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 21/23] dmaengine: sdxi: Add unit tests for descriptor encoding Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 22/23] dmaengine: sdxi: MSI/MSI-X vector allocation and mapping Nathan Lynch via B4 Relay
2026-05-11 19:16 ` [PATCH v2 23/23] dmaengine: sdxi: Add DMA engine provider Nathan Lynch via B4 Relay
2026-05-11 20:47 ` Frank Li
2026-05-11 22:28 ` Lynch, Nathan
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