From: sashiko-bot@kernel.org
To: "Richard Zhu" <hongxing.zhu@nxp.com>
Cc: robh@kernel.org, Frank.Li@kernel.org, imx@lists.linux.dev,
krzk+dt@kernel.org, linux-pci@vger.kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
Date: Thu, 14 May 2026 01:04:47 +0000 [thread overview]
Message-ID: <20260514010447.A329CC19425@smtp.kernel.org> (raw)
In-Reply-To: <20260513025101.1498104-2-hongxing.zhu@nxp.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Strictly ordered `items` array prevents omitting intermediate optional interrupts.
- [Medium] Global addition of optional interrupts loosens schema validation for older hardware generations.
--
commit c716cc823581eb06c45ae0ee7c1441e2e4b80ec3
Author: Richard Zhu <hongxing.zhu@nxp.com>
dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
This commit adds optional interrupt entries (intr, aer, pme) to the i.MX6Q
PCIe binding to support event-based interrupt handling.
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 9d1349855b422..cf709132ff1e2 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -58,12 +58,18 @@ properties:
> items:
> - description: builtin MSI controller.
> - description: builtin DMA controller.
> + - description: PCIe event interrupt.
> + - description: builtin AER SPI standalone interrupt line.
> + - description: builtin PME SPI standalone interrupt line.
By adding these optional interrupts at the top level, the maximum number
of interrupts implicitly increases from 2 to 5 for all compatible strings
in this binding.
Will this allow older hardware generations that physically only support
2 interrupts to silently pass validation if they incorrectly specify up to 5?
Should the existing allOf conditional blocks explicitly restrict maxItems
for the interrupts property on variants lacking these new capabilities?
>
> interrupt-names:
> minItems: 1
> items:
> - const: msi
> - const: dma
> + - const: intr
> + - const: aer
> + - const: pme
If a hardware variant supports the msi and intr interrupts but lacks the
optional dma interrupt, won't this strict array validation fail?
Since dt-schema enforces exact positional matching for items arrays, a device
tree specifying interrupt-names = "msi", "intr" would have the "intr" entry
evaluated against the second constraint (- const: dma).
Does this need an enum/anyOf structure with minItems/maxItems, or specific
allOf conditionals per SoC to correctly handle omitting intermediate entries?
>
> reset-gpio:
> description: Should specify the GPIO for controlling the PCI bus device
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260513025101.1498104-1-hongxing.zhu@nxp.com?part=1
next prev parent reply other threads:[~2026-05-14 1:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 2:50 [PATCH v4 0/3] Add root port reset to support link recovery Richard Zhu
2026-05-13 2:50 ` [PATCH v4 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts Richard Zhu
2026-05-14 1:04 ` sashiko-bot [this message]
2026-05-13 2:51 ` [PATCH v4 2/3] arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe Richard Zhu
2026-05-13 2:51 ` [PATCH v4 3/3] PCI: imx6: Add root port reset to support link recovery Richard Zhu
2026-05-13 3:32 ` Bough Chen
2026-05-13 7:41 ` Hongxing Zhu
2026-05-14 2:06 ` sashiko-bot
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