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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FYfvMSfZBXMBkQuv6NqJ61Hn/6Ji/iL82rD+JOtyOXSFQaue5pHkylAjUM38b5rgC6xLVsjQ243GkNRFX/LaqAevMxDvMQqlfIROoDuv/M9qurjQeMT+Yrd4Vns6edi+eOJp9R3wu51pvf6KINUKBrcSFHdJgtbOrs1qC0CkpS295b0ru+eIBS/C5oDXyM9AvxDhwN/20tx59JiDJwVJkOcHV4lLmS4xMx4/1bFXqTDPGF2d1ewv4DeCVEZYhQpe7Qus5bxw7TqToaXYMqMYcYNGWEGfQFqUPW1AWnaDTVqy4moZ43PpzJdnGCDuvy2EbfUilDaKzm28ZvKo6ebYAG06BW3DOO7G3H+wS2+Ovhh4lnLeIwIrjZ+Mv1o7Ty6JDNBIcUZbkKE5mMggdn/1goJOWjbO3YaOzHZ1f1AY5rYW15UWIj0g6d7cEk8DoaSC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2026 07:08:36.0641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 547c9b00-996f-4053-7414-08deb250c860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7352 This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA Tegra194/234 PCIe controllers from an optional device tree property and corrects the default nanosecond cells so the PORT_AFR field advertises the intended latency buckets. Background ---------- The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI), bits 27:29. Software must select a 3-bit code for the maximum L1 entry delay the platform can tolerate. Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds), converts to whole microseconds with ceiling division (DIV_ROUND_UP), and programs min(order_base_2(us), 7) into PORT_AFR during ASPM init. If the property is absent, the driver keeps the existing default (code 7). PORT_AFR L1 entrance latency encoding (bits 27:29) -------------------------------------------------- +--------------------------+----------+ | Advertised maximum | Code | +--------------------------+----------+ | Maximum of 1 us | 000b | +--------------------------+----------+ | Maximum of 2 us | 001b | +--------------------------+----------+ | Maximum of 4 us | 010b | +--------------------------+----------+ | Maximum of 8 us | 011b | +--------------------------+----------+ | Maximum of 16 us | 100b | +--------------------------+----------+ | Maximum of 32 us | 101b | +--------------------------+----------+ | Maximum of 64 us | 110b | +--------------------------+----------+ | Rest | 111b | +--------------------------+----------+ Patch summary ------------- 1/2 PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency Add driver support described above. v1 and v2 could not program encoding 0 (000b, 1 us bucket); v3 uses order_base_2(us) so values map to the table. 2/2 arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells Commit d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes") added 4000 / 8000 / 16000 ns cells. After ceiling conversion those are 4 / 8 / 16 us, yielding PORT_AFR codes 2 / 3 / 4. The intended advertisement is codes 3 / 4 / 5 (8 / 16 / 32 us buckets). Double each nanosecond cell: tegra194.dtsi: 4000 -> 8000 ns (all Root Port and Endpoint nodes) tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint) With the v3 driver mapping in place, the original nanosecond cells no longer yield the intended PORT_AFR codes; doubling them restores codes 3 / 4 / 5 as described above. Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes") Testing ------- - Verified device tree parsing and PORT_AFR encoding on target hardware. - Exercised boundary nanosecond values with a temporary debug patch. - Built on x86_64 (previous revision exposed a tree build failure). Manikanta Maddireddy (2): PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++------ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 +++++++++++----------- drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++ 3 files changed, 38 insertions(+), 25 deletions(-) -- 2.34.1