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Sat, 16 May 2026 18:49:19 -0700 (PDT) Received: from localhost ([2001:19f0:8001:1b2d:5400:5ff:fefa:a95d]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19778ad1sm10531320b3a.17.2026.05.16.18.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 May 2026 18:49:19 -0700 (PDT) From: Inochi Amaoto To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , Christian Bruel , Vincent Guittot , Senchuan Zhang , Alex Elder , Nam Cao , Siddharth Vadapalli , Randolph Lin , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v2 2/5] PCI: spacemit-k1: Add multiple PHY handles support Date: Sun, 17 May 2026 09:48:37 +0800 Message-ID: <20260517014841.254085-3-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517014841.254085-1-inochiama@gmail.com> References: <20260517014841.254085-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The PCIe controller on Spacemit K3 may use multiple PHYs at the same time. The feature is not support by the current driver. So extend the PHY definition to support multiple PHY handles. Signed-off-by: Inochi Amaoto --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c index 1b519d49dcc0..7f6f1df31cd8 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -51,7 +51,8 @@ struct k1_pcie { struct dw_pcie pci; - struct phy *phy; + struct phy **phy; + int phy_count; void __iomem *link; struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ u32 pmu_off; @@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) */ regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); - ret = phy_init(k1->phy); + ret = phy_init(k1->phy[0]); if (ret) { k1_pcie_disable_resources(k1); @@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct k1_pcie *k1 = to_k1_pcie(pci); + int i; /* Assert fundamental reset (drive PERST# low) */ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, PCIE_RC_PERST); - phy_exit(k1->phy); + for (i = 0; i < k1->phy_count; i++) + phy_exit(k1->phy[i]); k1_pcie_disable_resources(k1); } @@ -277,7 +280,12 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) if (IS_ERR(phy)) return PTR_ERR(phy); - k1->phy = phy; + k1->phy = devm_kmalloc_array(dev, 1, sizeof(*k1->phy), GFP_KERNEL); + if (!k1->phy) + return -ENOMEM; + + k1->phy[0] = phy; + k1->phy_count = 1; return 0; } -- 2.54.0