From: Bjorn Helgaas <helgaas@kernel.org>
To: Alex Williamson <alex@shazbot.org>
Cc: Ankit Agrawal <ankita@nvidia.com>,
kvm@vger.kernel.org, jgg@ziepe.ca, yishaih@nvidia.com,
skolothumtho@nvidia.com, kevin.tian@intel.com,
bhelgaas@google.com, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v7 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC
Date: Mon, 8 Jun 2026 10:47:05 -0500 [thread overview]
Message-ID: <20260608154705.GA36965@bhelgaas> (raw)
In-Reply-To: <20260528115613.63f1b178@shazbot.org>
On Thu, May 28, 2026 at 11:56:13AM -0600, Alex Williamson wrote:
> On Thu, 28 May 2026 09:38:40 +0000
> Ankit Agrawal <ankita@nvidia.com> wrote:
> ...
> > drivers/vfio/pci/nvgrace-gpu/main.c | 144 ++++++++++++++++++++++++++--
> > include/uapi/linux/pci_regs.h | 1 +
>
> Bjorn, I assume you don't object to this trivial addition:
>
> > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> > index 14f634ab9350..718fb630f5bb 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -1357,6 +1357,7 @@
> > #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
> > #define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0)
> > #define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1)
> > +#define PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT __GENMASK(15, 13)
> > #define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
> > #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
> > #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
Yep, looks fine to me.
prev parent reply other threads:[~2026-06-08 15:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 9:38 [PATCH v7 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC Ankit Agrawal
2026-05-28 10:22 ` sashiko-bot
2026-05-28 17:56 ` Alex Williamson
2026-05-29 11:27 ` Ankit Agrawal
2026-06-08 15:47 ` Bjorn Helgaas [this message]
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