From: Bjorn Helgaas <helgaas@kernel.org>
To: Sumedh Thakre <tsunedh74@gmail.com>
Cc: lpieralisi@kernel.org, bhelgaas@google.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] PCI: dwc: custom-arm: reduce bus enumeration latency by ~15%
Date: Mon, 8 Jun 2026 10:59:40 -0500 [thread overview]
Message-ID: <20260608155940.GA37162@bhelgaas> (raw)
In-Reply-To: <CAJkrBpvmxxfmnj4iwuxqEhAxUJrt4EOXmM7=sX=aNHjN8te2aw@mail.gmail.com>
On Mon, Jun 01, 2026 at 11:24:45PM +0530, Sumedh Thakre wrote:
> Hi Lorenzo and Bjorn,
>
> I'd like to submit a two-patch series that fixes three independent boot-time
> latency regressions in the custom ARM DesignWare PCIe root complex driver
> and
> its companion device tree.
>
> The patches reduce PCIe bus enumeration time by ~15% (7,100 µs mean
> improvement across 500 cold-boot cycles) on a Cortex-A55 / DesignWare Gen3 /
> NVMe platform:
>
> Root cause | Component | Savings
> ------------------------------------|-----------|--------
> Double PHY reset via .host_init() | Driver | ~8 ms
> Sequential PHY + clock init (DTS) | DTS | ~5 ms
> 1 ms link-up poll on 2–4 ms hw link | Driver | ~2 ms
>
> Baseline: 47,300 µs ±820 µs (n=500)
> Patched : 40,200 µs ±610 µs (n=500)
>
> Patch 1/2 adds a phy_initialized guard to prevent double PHY reset and
> introduces a platform-specific 250 µs link-up polling interval
> (compliant with PCIe Base Spec 4.0 §6.6.1).
>
> Patch 2/2 corrects the device tree to declare explicit PHY clock parents
> (enabling parallel probe), adds the required REFCLK stagger margin
> (250 ns, fixes sporadic LTSSM failures below 10 °C), and aligns
> PERST# assert timing and poll properties with the driver changes.
>
> Both patches are independently bisectable. The series has been tested with:
> - 500 cold-boot iteration benchmark (ftrace timestamps)
> - dtc validation and dt_binding_check
> - dt-validate against dt-schema
> - Sparse (make C=1): no new warnings
> - checkpatch.pl: 0 errors, 0 warnings
>
> The patches are attached to this email and are also available at:
>
> https://github.com/tsunedh74-droid/linux-pcie-custom-arm-latency-fix/tree/main
If it's possible to send the patches directly as responses (not
attachments), that would be better:
https://people.kernel.org/tglx/notes-about-netiquette
Looking at the github tree, the patches touch
drivers/pci/controller/dwc/pcie-custom-arm.c and
arch/arm64/boot/dts/vendor/custom-arm-pcie.dts. Neither exists
upstream. Maybe this work is based on some downstream tree that
includes a driver that isn't yet upstream?
prev parent reply other threads:[~2026-06-08 15:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-01 17:54 [PATCH 0/2] PCI: dwc: custom-arm: reduce bus enumeration latency by ~15% Sumedh Thakre
2026-06-08 15:59 ` Bjorn Helgaas [this message]
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