Linux PCI subsystem development
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From: sashiko-bot@kernel.org
To: "Gowtham Kudupudi" <gowtham@ferryfair.com>
Cc: neil.armstrong@linaro.org, linux-amlogic@lists.infradead.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI: meson: Fix PERST# timing by asserting reset before LTSSM enable
Date: Sun, 14 Jun 2026 02:31:39 +0000	[thread overview]
Message-ID: <20260614023139.A51F41F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260614015620.20432-1-gowtham@ferryfair.com>

> On warm reboot, the PCIe controller's LTSSM starts link training
> immediately if PERST# is already deasserted from the previous boot.
> The driver then pulses PERST# for only 500us, which is too short to
> properly reset the endpoint device that has already started training.
> 
> Fix by moving the PERST# assert/deassert pulse BEFORE enabling LTSSM,
> so the endpoint gets a clean reset cycle before link training begins.
> 
> This was found on Amlogic G12B (A311D) with NVMe on an M.2 slot.
> Cold boot worked because POR held PERST# low; warm reboot did not.
> The fix was confirmed on a Banana Pi CM4 with Waveshare IO base board.
> 
> Signed-off-by: Gowtham Kudupudi <gowtham@ferryfair.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260614015620.20432-1-gowtham@ferryfair.com?part=1


       reply	other threads:[~2026-06-14  2:31 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20260614015620.20432-1-gowtham@ferryfair.com>
2026-06-14  2:31 ` sashiko-bot [this message]
2026-06-15 10:34 ` [PATCH] PCI: meson: Fix PERST# timing by asserting reset before LTSSM enable Ronald Claveau
2026-06-16  6:06   ` neil.armstrong
2026-06-16 23:36     ` gowtham

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