From: kangfenglong <kangfenglong@huawei.com>
To: <kbusch@kernel.org>
Cc: <linux-nvme@lists.infradead.org>, <linux-pci@vger.kernel.org>,
<liuyonglong@huawei.com>, <seven.wangyu@huawei.com>,
<kangfenglong@huawei.com>
Subject: [PATCH v2] nvme-pci: fix CMB mapping when CMBSZ Size field is zero
Date: Mon, 22 Jun 2026 09:21:47 +0800 [thread overview]
Message-ID: <20260622012147.40600-1-kangfenglong@huawei.com> (raw)
The controller memory buffer size is defined by the SZ field in the
CMBSZ register (bits 31:12). According to the NVMe specification, a
value of zero in the SZ field indicates that no CMB is present.
Commit f65efd6dfe4e ("nvme-pci: clean up CMB initialization") replaced
the check for a zero SZ field with a check for a zero CMBSZ register
value, under the assumption that a zero register implies no CMB.
However, a CMBSZ register can be non-zero while the SZ field is zero,
for example when Size Units (SZU) is set to a non-zero value but the
actual size is zero (e.g. CMBSZ = 0x100: SZU = 1, SZ = 0).
When this happens, nvme_map_cmb() proceeds to compute a size of zero,
passes the alignment checks (zero is always aligned), and calls
pci_p2pdma_add_resource() with size=0. The P2PDMA subsystem then
defaults size to the entire remaining BAR, which may not be properly
aligned for memory hotplug, triggering:
WARNING: CPU: 0 PID: 10 at mm/memory_hotplug.c:396 __add_pages
Misaligned __add_pages start: 0x494a0000 end: 0x494a000f
Fix this by:
1. Restoring the check for a zero SZ field, which explicitly verifies
that the controller actually has a CMB before proceeding.
2. Adding a boundary check in nvme_cmb_size_unit() to reject SZU values
greater than 6. The SZU field is 4 bits, but values 7-15 are reserved
by the NVMe specification and produce a shift count >= 40 in the
left-shift operation (1ULL << (12 + 4 * szu) when szu >= 7), which
exceeds the maximum 64 GB unit size defined by the spec.
3. Using check_mul_overflow() for the size calculation to detect integer
overflow that could wrap to a non-zero value and bypass the SZ check.
Fixes: f65efd6dfe4e ("nvme-pci: clean up CMB initialization")
Signed-off-by: kangfenglong <kangfenglong@huawei.com>
---
drivers/nvme/host/pci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 8438c904ec49..5c7b1e757e4d 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2448,6 +2448,9 @@ static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
{
u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
+ if (szu > 6)
+ return 0;
+
return 1ULL << (12 + 4 * szu);
}
@@ -2472,9 +2475,12 @@ static void nvme_map_cmb(struct nvme_dev *dev)
dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
if (!dev->cmbsz)
return;
+ if (!nvme_cmb_size(dev))
+ return;
dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
- size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
+ if (check_mul_overflow(nvme_cmb_size_unit(dev), nvme_cmb_size(dev), &size))
+ return;
offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
bar = NVME_CMB_BIR(dev->cmbloc);
bar_size = pci_resource_len(pdev, bar);
--
2.12.0.windows.1
next reply other threads:[~2026-06-22 1:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 1:21 kangfenglong [this message]
2026-06-22 1:28 ` [PATCH v2] nvme-pci: fix CMB mapping when CMBSZ Size field is zero sashiko-bot
2026-06-22 2:39 ` 答复: " Kangfenglong
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