[PATCH v7 11/11] Documentation/ABI: Document CXL Reset PCI reset method

[Srirangan Madhavan <smadhavan@nvidia.com>]

Document the "cxl_reset" PCI reset_method value for Type 2 CXL devices.
CXL Reset is device scoped, requires affected memory to be idle,
invalidates CPU caches, restores cached HDM decoder state, and does not
request Memory Clear.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
 Documentation/ABI/testing/sysfs-bus-pci | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
index b767db2c52cb..dd8de5c7eb77 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -153,6 +153,20 @@ Description:
 		"default" enables all supported reset methods in the
 		default ordering.
 
+		If present, "cxl_reset" selects CXL Reset for CXL Type 2
+		devices that advertise CXL Reset support.  CXL Reset is device
+		scoped and affects all CXL.cache and CXL.mem functions.
+
+		Before issuing CXL Reset, the kernel quiesces affected PCI
+		functions, rejects the operation if affected CXL memory is busy,
+		invalidates CPU caches for enabled HDM ranges, disables
+		CXL.cache, and initiates cache write-back where supported.  After
+		reset, the kernel restores PCI config state to access HDM MMIO,
+		restores cached HDM decoder state, and then completes reset
+		recovery for the affected functions.  If cached HDM decoder
+		state is unavailable at reset time, the kernel skips this reset
+		method.  "cxl_reset" does not request CXL Reset Memory Clear.
+
 What:		/sys/bus/pci/devices/.../reset
 Date:		July 2009
 Contact:	Michael S. Tsirkin <mst@redhat.com>
-- 
2.43.0