Re: [PATCH v2] pci: loongson: Avoid L0s on LS7A1000 PCIe x8 [0014:7a29] Root Ports rev2

[sashiko-bot@kernel.org]

> Commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> devicetree platforms") has broke booting of a Loongson 3B4000 + 7A1000
> server with an Intel 750 Series SSD.  We also found a Loongson 3A5000
> board using the same 7A1000 bridge chip exhibiting the same issue with
> pcie_aspm=force and pcie_aspm.policy=powersave (ASPM is not enabled by
> default on the 3A5000 board because it's based on ACPI and the _OSC
> method has not been implemented in its DSDT/SSDT yet).
> 
> This seems only affecting the 7A1000 chips shipping the revision 2 of
> the PCIe x8 Root Port: on other two boards with a (persumably older)
> LS7A1000 bridge chip utilizing the revision 1 of the root port, the
> issue does not reproduce.
> 
> Cc: Mingcong Bai <jeffbai@aosc.io>
> Cc: Henry Chen <chenx97@aosc.io>
> Cc: Han Gao <gaohan@iscas.ac.cn>
> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> Signed-off-by: Xi Ruoyao <xry111@xry111.site>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260623173648.222922-1-xry111@xry111.site?part=1