Re: [PATCH v5 17/18] iommu/arm-smmu-v3: Thread arm_smmu_master_domain on a per-master list

[sashiko-bot@kernel.org]

> A subsequent change needs to enumerate, from the CMDQ error path in atomic
> context, every domain a master is attached to so it can mark this master's
> ATS entries broken in each domain's invs after an ATC invalidation timeout.
> The existing per-domain smmu_domain->devices list tracks the inverse
> direction (masters in a given domain), so introduce a per-master list.
> 
> Add a second list_head master_elm to arm_smmu_master_domain, threaded onto
> a new master->master_domains list under master_domains_lock. The CMDQ error
> path walks the list while holding smmu->streams_lock; that path runs under
> the invs->rwlock read side, which is itself sleepable on PREEMPT_RT, so a
> plain spinlock_t suffices for both. The attach and detach sites now take it
> with spin_lock(), nested inside the existing devices_lock critical section
> that already disables IRQs; it is a leaf in the lock order, so no inversion
> is introduced.
> 
> No functional change.
> 
> Assisted-by: Claude:claude-opus-4-7
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1783044582.git.nicolinc@nvidia.com?part=17