From: sashiko-bot@kernel.org
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>
Cc: linux-pci@vger.kernel.org, vkoul@kernel.org,
linux-phy@lists.infradead.org, olteanv@gmail.com,
neil.armstrong@linaro.org
Subject: Re: [PATCH v3 4/4] PCI: qcom: enable Link retain logic for Hamoa
Date: Thu, 09 Jul 2026 07:02:48 +0000 [thread overview]
Message-ID: <20260709070248.A296A1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260709-link_retain-v3-4-81a9d187bb61@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Probe deferral leaks PHY power-on, clock, and regulator enable counts when `link_retain` is active.
--
--- Patch [4]: [PATCH v3 4/4] PCI: qcom: enable Link retain logic for Hamoa ---
commit a80ea22accc5e92e309b80e7933e0f0bac88c9ec
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
PCI: qcom: enable Link retain logic for Hamoa
The Hamoa platform supports keeping the PCIe link active across
bootloader and kernel handoff. To take advantage of this, introduce a
specific configuration (cfg_x1e80100) with link_retain = true and
update the device match table to use it.
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 77d2d989e9da5..0b345a16f4cf6 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1671,6 +1671,12 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = {
> .no_l0s = true,
> };
>
> +static const struct qcom_pcie_cfg cfg_x1e80100 = {
> + .ops = &ops_1_21_0,
> + .no_l0s = true,
> + .link_retain = true,
[Severity: High]
Does enabling link_retain here cause a resource leak during probe deferral?
In qcom_pcie_host_init(), if an initialization step returns -EPROBE_DEFER and
link_retain is true, the error path returns early:
drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_host_init() {
...
err_pwrctrl_destroy:
if (pp->link_retain && ret == -EPROBE_DEFER)
return ret;
...
}
This bypasses err_disable_phy and err_deinit which would balance the
resource counts.
Since qcom_pcie_init_2_7_0() unconditionally enables the regulators and
clocks, and qcom_pcie_phy_power_on() enables the PHYs, won't these reference
counts be leaked on each deferral retry? When the driver is eventually
removed, deinit() will only decrement them once, leaving the resources
permanently enabled.
Is there a way to balance these reference counts during a probe deferral
when link_retain is active?
> +};
> +
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260709-link_retain-v3-0-81a9d187bb61@oss.qualcomm.com?part=4
next prev parent reply other threads:[~2026-07-09 7:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 6:35 [PATCH v3 0/4] PCI: qcom: Add link retention support Krishna Chaitanya Chundru
2026-07-09 6:35 ` [PATCH v3 1/4] phy: qcom: qmp-pcie: Skip PHY reset if already up Krishna Chaitanya Chundru
2026-07-09 6:47 ` sashiko-bot
2026-07-09 6:35 ` [PATCH v3 2/4] PCI: qcom: Keep PERST# GPIO state as-is during probe Krishna Chaitanya Chundru
2026-07-09 6:44 ` sashiko-bot
2026-07-09 6:35 ` [PATCH v3 3/4] PCI: qcom: Add link retention support Krishna Chaitanya Chundru
2026-07-09 6:53 ` sashiko-bot
2026-07-09 6:35 ` [PATCH v3 4/4] PCI: qcom: enable Link retain logic for Hamoa Krishna Chaitanya Chundru
2026-07-09 7:02 ` sashiko-bot [this message]
2026-07-09 13:19 ` Konrad Dybcio
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