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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF00002319.mail.protection.outlook.com (10.167.242.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 22:28:45 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 17:28:43 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 08/13] cxl/pci: Thread port and dport through RAS handling helpers Date: Fri, 17 Jul 2026 17:27:01 -0500 Message-ID: <20260717222706.3540281-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002319:EE_|CH1PPF84B7B0C96:EE_ X-MS-Office365-Filtering-Correlation-Id: 03f9441c-65aa-448d-c6bc-08dee452c3ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|36860700016|82310400026|1800799024|10067099003|6133799003|56012099006|22082099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: CbqYr+kY/IgsXX1RSccqFz3lKtzHOYZv7GP2hK/QmKP9xRVzgur6oXsl0OQGJJjqnCjlKzX4MZ6dc/7OzlX5kmOlliFkVgai0xSGAcsyRKh46PK4F5pVjAiD/Ev5ZrdYD18zWR/OstWBvI/6hwXZ0g5rIO/oRqPJzN6iv8ZuONqdtHFJH6pSGp7c3Udj8UE1NC9Z7r7u6O578slTM+cizsQ4wKwuf/CSry9E8zP1Hj8HBRfkzOWh6/EXu+Talfz4TMygEYpcTB2KkFy/89ZqtIe4X1v8yrXwK6mw+m94kEUc+wo1cSkgd+Y/B9JrgctVBqrZn/sGrEdhKIXlmsnTbly/RhSk0WK68NXUeBSVxF6moQL1nFqZLlMvcHn0Sb56FP3J23F5exUOX+6pWSGDYZp+foFbLQ69tF6LsBMysLjqCVbTdn5KZ88qD2w5Co/NNfXNNGW9L8ctbLJPjOGrqQPeD88hsrq96AeEHpOhKhte7Win6eR+/I2WYQu7+zpBbQSsAZPzFc9S/UH6OXAfUTf4zVusFqaArBU3Vg8WzHfw+q0euQDuwQEN2yyE6NKWyPmcfryfzlW02Z8m+dUbKmLskRM3tNxsq704Zd9tvNwIFrm1UguDpsO5pnRH/jcRn5CzwSBzjEiZzhTE4zbOhfovKkPrrBTT1V2F1x+M8h0Hz6i0+dwXzIHf9NWvzxWwsPBL5EplMsndra/KOx08yw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(376014)(36860700016)(82310400026)(1800799024)(10067099003)(6133799003)(56012099006)(22082099003)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9mVrq4ePbfxXja9NrMW/sws2QQjBmvf4sy5YD+2r80mMyYFFLENFBQzzrEaILCahpxcJi0+NGwO0/JcKUxoj64KrmjvuJcFKpT9HwxtS4ztqcY8s0YwjotSyqg8C7nc2S6qGccgnTbyipoLP1qnPkHi2pVfeDJbdV+500g/zmfVuknBiygwzK1u4UayhG3SqCJEum/RSOkCR2pHompIxxYMbRbV6SehJeN1N0s7l1x3+NZ9J6qvH7lLYjSRQydglFfyHs4mZN889bQw4fJXxOap+evo/RxmudtMaSxbncgsDYpD1WnKYVkLyyx6YsvZEkeI+hy/TIfKWDcGLLwV3VqF8CvJNjNIxvDZALxhQhZjxzY0D0E67ZUt1mnLnZGz8iw/KSj9N7VyH/T3ZMXFGWgud5SiJgiWzd5x0XJ7SZuhHnYDcbys0/z1YY7WPKpTM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:28:45.3215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03f9441c-65aa-448d-c6bc-08dee452c3ac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF84B7B0C96 From: Dan Williams The callers of cxl_handle_ras() and cxl_handle_cor_ras() already hold a struct cxl_port * and struct cxl_dport * for the device being handled. Passing a generic struct device * requires is_cxl_memdev() to distinguish Endpoints from ports at trace emission time. Threading port and dport directly enables is_cxl_endpoint(port) and explicit dport/port branching for cleaner trace dispatch. Refactor cxl_handle_ras() and cxl_handle_cor_ras() to accept struct cxl_port * and struct cxl_dport * directly. The CXL RAS trace event emission logic is split into three branches: Endpoint events are identified via is_cxl_endpoint(port) and emit with the memdev, dport events emit with dport->dport_dev, and Upstream Port events fall back to port->uport_dev. Update cxl_handle_rdport_errors() in ras_rch.c and cxl_handle_proto_error() in ras.c to pass port and dport to the refactored functions. RCH Downstream Port correctable trace events now report the dport device (dport->dport_dev) as a consequence of threading port and dport through the RAS helpers. The following trace event rework ("cxl: Add port and dport identifiers to CXL AER trace events") adds explicit memdev, port, dport, and host fields that provide full context for all device types. Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Dan Williams --- Changes in v17 -> v18: - New patch. --- drivers/cxl/core/core.h | 12 ++++++++---- drivers/cxl/core/ras.c | 29 +++++++++++++++-------------- drivers/cxl/core/ras_rch.c | 2 +- 3 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 272634ff2615b..5ca1275fd8f35 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -185,10 +185,12 @@ static inline struct device *dport_to_host(struct cxl_dport *dport) #ifdef CONFIG_CXL_RAS void cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base); void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport); -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct pci_dev *pdev); @@ -197,13 +199,15 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport); #else static inline void cxl_ras_init(void) { } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base) { return false; } static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport) { } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { } +static inline void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 9a142abcf4f8b..6f4a3c1b0bb85 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -232,7 +232,6 @@ void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport) void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport) { - struct device *dev = dport ? dport->dport_dev : port->uport_dev; void __iomem *ras_base = to_ras_base(port, dport); if (!ras_base) { @@ -241,14 +240,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dpo return; } - if (cxl_handle_ras(dev, ras_base)) + if (cxl_handle_ras(port, dport, ras_base)) panic("CXL cachemem error"); dev_dbg(&pdev->dev, "CXL UCE signaled but no CXL RAS status bits set\n"); } -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base) { u32 status; void __iomem *addr; @@ -260,10 +259,12 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) status = readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - if (is_cxl_memdev(dev)) - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + if (is_cxl_endpoint(port)) + trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status); + else if (dport) + trace_cxl_port_aer_correctable_error(dport->dport_dev, status); else - trace_cxl_port_aer_correctable_error(dev, status); + trace_cxl_port_aer_correctable_error(port->uport_dev, status); } } @@ -288,7 +289,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {}; void __iomem *addr; @@ -315,10 +316,12 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) } header_log_copy(ras_base, hl); - if (is_cxl_memdev(dev)) - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_endpoint(port)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status, fe, hl); + else if (dport) + trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, status, fe, hl); else - trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); @@ -351,7 +354,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue = cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL)); + ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL)); } /* @@ -382,10 +385,8 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport, int severity) { - struct device *dev = dport ? dport->dport_dev : port->uport_dev; - if (severity == AER_CORRECTABLE) - cxl_handle_cor_ras(dev, to_ras_base(port, dport)); + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport)); else cxl_do_recovery(pdev, port, dport); } diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index f2d2fb83758b9..f4b98f2c11a1c 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -118,7 +118,7 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) pci_print_aer(pdev, severity, &aer_regs); if (severity == AER_CORRECTABLE) - cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport)); + cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport)); else cxl_do_recovery(pdev, dport->port, dport); } -- 2.34.1