From: sashiko-bot@kernel.org
To: "Nirmoy Das" <nirmoyd@nvidia.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [RFC PATCH] PCI: Work around Pericom PI7C9X3G606GPC Port 4 BAR erratum
Date: Thu, 23 Jul 2026 16:16:51 +0000 [thread overview]
Message-ID: <20260723161704.B869C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260723161010.2638956-1-nirmoyd@nvidia.com>
> The Pericom PI7C9X3G606GPC PCIe switch has an erratum where downstream
> Port 4 retains a default MSI-X table and PBA decode when BAR 0 is zero.
> Memory reads that match this window are dropped with an Unsupported
> Request completion, which may cause the SoC to report a timeout.
>
> The workaround is to make Port 4 BAR 0 mirror BAR 0 of the immediate
> upstream port. Firmware may establish this at boot, but PCI resource
> assignment can move upstream BAR 0 without updating Port 4.
>
> For a 64-bit BAR, also mirror BAR 1 while memory decoding is disabled,
> matching the PCI core update sequence. Port 4 BAR 0 may read back as zero
> after a successful write, so do not use readback to validate the update.
>
> Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260723161010.2638956-1-nirmoyd@nvidia.com?part=1
next prev parent reply other threads:[~2026-07-23 16:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 16:10 [RFC PATCH] PCI: Work around Pericom PI7C9X3G606GPC Port 4 BAR erratum Nirmoy Das
2026-07-23 16:16 ` sashiko-bot [this message]
2026-07-23 20:54 ` Bjorn Helgaas
2026-07-24 8:36 ` JC Chen[陳饒靜]
2026-08-26 14:28 ` Ilpo Järvinen
2026-08-27 0:13 ` JC Chen[陳饒靜]
2026-08-27 6:45 ` JC Chen[陳饒靜]
2026-08-31 15:29 ` Nirmoy Das
2026-09-01 2:51 ` JC Chen[陳饒靜]
2026-09-02 19:08 ` Nirmoy Das
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