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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF0000B373.mail.protection.outlook.com (10.167.243.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.1 via Frontend Transport; Tue, 28 Jul 2026 09:17:55 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 28 Jul 2026 04:17:55 -0500 Received: from xhddevverma40x.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Tue, 28 Jul 2026 04:17:52 -0500 From: Devendra K Verma To: , , CC: , , , , , Subject: [PATCH v2 1/3] dmaengine: dw-edma: Make Xilinx Macros Dev Name Agnostic Date: Tue, 28 Jul 2026 14:47:42 +0530 Message-ID: <20260728091744.1086942-2-devverma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260728091744.1086942-1-devverma@amd.com> References: <20260728091744.1086942-1-devverma@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B373:EE_|IA0PR12MB8228:EE_ X-MS-Office365-Filtering-Correlation-Id: fed22401-dd5d-49f3-f120-08deec891c08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|376014|36860700016|82310400026|10067099003|11063799006|56012099006|18002099003|22082099003; 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Renamed the Xilinx specific macros in a way that can be reused for Xilinx supported upcoming IP, CPM6. Naming is in accordance with the naming done for Synopsys macros. Signed-off-by: Devendra K Verma --- Changes in v1: o No change --- drivers/dma/dw-edma/dw-edma-pcie.c | 58 +++++++++++++++--------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 791c46e8ae4c..ec5e057a0f11 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -29,21 +29,21 @@ #define PCI_DEVICE_ID_XILINX_B054 0xb054 #define PCI_DEVICE_ID_XILINX_B00F 0xb00f -#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 -#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 -#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) - -#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc -#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8 -#define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL) - -#define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000 -#define DW_PCIE_XILINX_MDB_LL_SIZE 0x800 -#define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000 -#define DW_PCIE_XILINX_MDB_DT_SIZE 0x800 +#define DW_PCIE_XILINX_VSEC_DMA_ID 0x6 +#define DW_PCIE_XILINX_VSEC_ID 0x20 +#define DW_PCIE_XILINX_VSEC_DMA_BAR GENMASK(10, 8) +#define DW_PCIE_XILINX_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_XILINX_VSEC_DMA_WR_CH GENMASK(9, 0) +#define DW_PCIE_XILINX_VSEC_DMA_RD_CH GENMASK(25, 16) + +#define DW_PCIE_XILINX_DEVMEM_OFF_REG_HIGH 0xc +#define DW_PCIE_XILINX_DEVMEM_OFF_REG_LOW 0x8 +#define DW_PCIE_XILINX_INVALID_ADDR (~0ULL) + +#define DW_PCIE_XILINX_LL_OFF_GAP 0x200000 +#define DW_PCIE_XILINX_LL_SIZE 0x800 +#define DW_PCIE_XILINX_DT_OFF_GAP 0x100000 +#define DW_PCIE_XILINX_DT_SIZE 0x800 #define DW_BLOCK(a, b, c) \ { \ @@ -258,10 +258,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, u16 vsec; u64 off; - pdata->devmem_phys_off = DW_PCIE_XILINX_MDB_INVALID_ADDR; + pdata->devmem_phys_off = DW_PCIE_XILINX_INVALID_ADDR; vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, - DW_PCIE_XILINX_MDB_VSEC_DMA_ID); + DW_PCIE_XILINX_VSEC_DMA_ID); if (!vsec) return; @@ -272,18 +272,18 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability DMA\n"); pci_read_config_dword(pdev, vsec + 0x8, &val); - map = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val); + map = FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_MAP, val); if (map != EDMA_MF_HDMA_NATIVE) return; pdata->mf = map; - pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_BAR, val); pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, - FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); + FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_WR_CH, val)); pdata->rd_ch_cnt = min(pdata->rd_ch_cnt, - FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val)); + FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_RD_CH, val)); pci_read_config_dword(pdev, vsec + 0x14, &val); off = val; @@ -293,16 +293,16 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pdata->rg.off = off; vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, - DW_PCIE_XILINX_MDB_VSEC_ID); + DW_PCIE_XILINX_VSEC_ID); if (!vsec) return; pci_read_config_dword(pdev, - vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH, + vsec + DW_PCIE_XILINX_DEVMEM_OFF_REG_HIGH, &val); off = val; pci_read_config_dword(pdev, - vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW, + vsec + DW_PCIE_XILINX_DEVMEM_OFF_REG_LOW, &val); off <<= 32; off |= val; @@ -360,7 +360,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, * address use the non-LL mode or simple mode supported by * the HDMA IP. */ - if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR) + if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_INVALID_ADDR) non_ll = true; /* @@ -370,10 +370,10 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, */ if (!non_ll) dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, - DW_PCIE_XILINX_MDB_LL_OFF_GAP, - DW_PCIE_XILINX_MDB_LL_SIZE, - DW_PCIE_XILINX_MDB_DT_OFF_GAP, - DW_PCIE_XILINX_MDB_DT_SIZE); + DW_PCIE_XILINX_LL_OFF_GAP, + DW_PCIE_XILINX_LL_SIZE, + DW_PCIE_XILINX_DT_OFF_GAP, + DW_PCIE_XILINX_DT_SIZE); } /* Mapping PCI BAR regions */ -- 2.43.0