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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF0000B36F.mail.protection.outlook.com (10.167.243.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.1 via Frontend Transport; Tue, 28 Jul 2026 09:17:58 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Tue, 28 Jul 2026 04:17:58 -0500 Received: from xhddevverma40x.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Tue, 28 Jul 2026 04:17:55 -0500 From: Devendra K Verma To: , , CC: , , , , , Subject: [PATCH v2 2/3] dmaengine: dw-edma: Enable Chan Separation via VSEC Date: Tue, 28 Jul 2026 14:47:43 +0530 Message-ID: <20260728091744.1086942-3-devverma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260728091744.1086942-1-devverma@amd.com> References: <20260728091744.1086942-1-devverma@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36F:EE_|SJ2PR12MB8062:EE_ X-MS-Office365-Filtering-Correlation-Id: 20c54957-6843-4f51-ad08-08deec891dbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|23010399003|1800799024|376014|10067099003|56012099006|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uFW9BBeu9JUWtyJWjTXLKIfk6UiCqlKxMN/14YtQQrGJgZgA6CHd0EdL2JojQCyc7u6x6/kHKZsQYr4twNvYq1WwJi1PJDJw1nZGEEuosaQbUpRRLwi9bRrX+txM2mYBKa8+lM+7iUgE0KukhomRbC9q0LO26D6Wrj9QTnbqpT9ofksPhXofdKlh2Lw2VBpu0Mh/mQDzbsMluvW+HCaFXBF3wpnHkdHZJPNyxX0a0zkQ73zAarIliogdvyim6vJLL00IZvwhZ4mjP3nryDjo23YudhOn2pwRtz+91j5/lOvcledvqXD31LLmwtWNdiYvGhV4zjR5LYSGk+eAoDUTzURJ0jSsnbpYlL1EzaAoew68wEKgZC1Oq6vnXQb9UaALWWqa4y4V2Ydirpv9hbKa0CFtY0VCEs7j/yiqMyzSD83V8xUs9pxxjSxzp8BNUOpO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2026 09:17:58.6414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20c54957-6843-4f51-ad08-08deec891dbd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8062 As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel register space separation from 256B to 32KB. Default supported size is 256B. Signed-off-by: Devendra K Verma --- Changes in v1: o Modified dw_edma_get_ch_sep_sz() as per review comment. The function now supports ch_sep_sz up to 32KB. o Updated to description to reflect the supported channel separation sizes. o Introduced the CPM6 specific macro for VSEC cap. --- drivers/dma/dw-edma/dw-edma-pcie.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index ec5e057a0f11..d0f209082878 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -31,8 +31,11 @@ #define DW_PCIE_XILINX_VSEC_DMA_ID 0x6 #define DW_PCIE_XILINX_VSEC_ID 0x20 -#define DW_PCIE_XILINX_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_XILINX_VSEC_DMA_BAR GENMASK(10, 8) +/* AMD CPM6 (Xilinx) supported cap */ +#define DW_PCIE_XILINX_CPM6_VSEC_CH_SEP GENMASK(18, 16) + #define DW_PCIE_XILINX_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_VSEC_DMA_RD_CH GENMASK(25, 16) @@ -73,6 +76,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + u32 ch_sep_sz; }; static const struct dw_edma_pcie_data snps_edda_data = { @@ -127,7 +131,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = { }; static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { - /* MDB registers location */ + /* CPM6 registers location */ .rg.bar = BAR_0, .rg.off = SZ_4K, /* 4 Kbytes */ .rg.sz = SZ_8K, /* 8 Kbytes */ @@ -189,6 +193,13 @@ static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); } +static u32 dw_edma_get_ch_sep_sz(u32 ch_sep_val) +{ + if (ch_sep_val > 0 && ch_sep_val <= 7) + return 256 << ch_sep_val; + return 256; +} + static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) { struct pci_dev *pdev = to_pci_dev(dev); @@ -279,6 +290,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pdata->mf = map; pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_BAR, val); + if (pdev->device == PCI_DEVICE_ID_XILINX_B00F) + pdata->ch_sep_sz = dw_edma_get_ch_sep_sz(FIELD_GET(DW_PCIE_XILINX_CPM6_VSEC_CH_SEP, + val)); + pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_WR_CH, val)); @@ -324,9 +339,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; struct device *dev = &pdev->dev; struct dw_edma_chip *chip; + bool non_ll = false; int err, nr_irqs; int i, mask; - bool non_ll = false; if (!pdata) return -ENODEV; -- 2.43.0