From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD9E132779D; Tue, 28 Jul 2026 15:53:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785254018; cv=none; b=SAXvZgK4I9GNJBn9GUeQVQSJy6xjiaf/kp/10aMBRZeya6n0hTr1twVOsCo7GfevgbZ2b/j+xr4sEcxIm0AaeH4GQ27G5DyxJc8cBgvum9ow9sZrRaWwfVmDGnZZ8DOY9EnFaeWQ1uWaVTUFgKQu2CjblqHlk1zL4fAZJwJ1WiA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785254018; c=relaxed/simple; bh=8PlIBJHI5XyC+hSKpOcHVDDAcCYXByfZtueiOfZ6khw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=doIQ08LmVy47DwZZnm0eromAxNzGuFeRuK/ZlxBtQA/0UECpzpI3R9dGIlOmOcToNUlFMFw2CwgnNo2IRgMKfjEaLo5OSEaq/Ikgcn9/lhxYh9NXvqAKJYq8H/8EHwNhR8zm+sGPR5qlf2dUpw9hT7GDHMfUoEgNPKiYTePA8Po= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Dd8ul8nN; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Dd8ul8nN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785254016; x=1816790016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8PlIBJHI5XyC+hSKpOcHVDDAcCYXByfZtueiOfZ6khw=; b=Dd8ul8nNRXgFttf+GMo+dpU/BGIB1cuyVFrOjuT5trMGgswGmHbNPlKh CbHCw6ZC+VhPGyMxz0xoxMVvEUkVvjb6rfTkaFKEv3BzyEy5rFU2r8Rhs 0eC736WkM7u/UgnCvQFjtZ697lEPFRcOgdCXomc6HUmDJCYJX4H9En4XI 1prj/LL0uwBMS3GudA59ju0z63RPpuT0/9P1RQyOOG3O+T9pUBpocNAsJ podH1lSm/xdeHb4xCNuppvw3+85pdh1Wd8qYbtW7JScBAih1DXBfEi/Bw w8E7F2Th2TPp0s6zh3lvd847u/ssL1ZmQ7KWkEGKSOH8htFTSy5tXIXYx g==; X-CSE-ConnectionGUID: 5qWTpJ7yRbicH2PwJvSR9A== X-CSE-MsgGUID: URAkHD6dTcyf9fnwj7YnKw== X-IronPort-AV: E=McAfee;i="6800,10657,11859"; a="85696770" X-IronPort-AV: E=Sophos;i="6.25,190,1779174000"; d="scan'208";a="85696770" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2026 08:53:36 -0700 X-CSE-ConnectionGUID: j/ycLldwRcuE9FZYPl/jiw== X-CSE-MsgGUID: hbzfLxyfTxi3Cxd8eVe5Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,190,1779174000"; d="scan'208";a="255817707" Received: from mkosciow-mobl1.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.126]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2026 08:53:34 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V2 7/8] i3c: mipi-i3c-hci: Factor out i3c_hci_sysdev() Date: Tue, 28 Jul 2026 18:53:07 +0300 Message-ID: <20260728155308.142713-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260728155308.142713-1-adrian.hunter@intel.com> References: <20260728155308.142713-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: 8bit The MIPI I3C HCI driver needs to identify the underlying system device used for DMA mapping and PM operations. The logic for determining that device is currently embedded in the DMA implementation. Factor this code out into i3c_hci_sysdev() so it can be shared by other parts of the driver and keep the device-selection logic in one place. Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/core.c | 12 ++++++++++++ drivers/i3c/master/mipi-i3c-hci/dma.c | 15 +-------------- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index cfe9b5390b56..0212c9e984cf 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -117,6 +118,17 @@ static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m) return container_of(m, struct i3c_hci, master); } +/* + * Determine the device that does PM / DMA and has IOMMU setup done for it in + * case of enabled IOMMU (for use with the DMA API). + * Such device is either "mipi-i3c-hci" platform device (OF/ACPI enumeration) + * parent or grandparent (PCI enumeration). + */ +struct device *i3c_hci_sysdev(struct device *dev) +{ + return dev->parent && dev_is_pci(dev->parent) ? dev->parent : dev; +} + static void i3c_hci_set_master_dyn_addr(struct i3c_hci *hci) { reg_write(MASTER_DEVICE_ADDR, diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mipi-i3c-hci/dma.c index 0672ed1132f8..7c2b20474130 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "hci.h" #include "cmd.h" @@ -301,23 +300,11 @@ static int hci_dma_init(struct i3c_hci *hci) { struct hci_rings_data *rings; struct hci_rh_data *rh; - struct device *sysdev; u32 regval; unsigned int i, nr_rings, xfers_sz, resps_sz; unsigned int ibi_status_ring_sz, ibi_data_ring_sz; int ret; - /* - * Set pointer to a physical device that does DMA and has IOMMU setup - * done for it in case of enabled IOMMU and use it with the DMA API. - * Here such device is either - * "mipi-i3c-hci" platform device (OF/ACPI enumeration) parent or - * grandparent (PCI enumeration). - */ - sysdev = hci->master.dev.parent; - if (sysdev->parent && dev_is_pci(sysdev->parent)) - sysdev = sysdev->parent; - regval = rhs_reg_read(CONTROL); nr_rings = FIELD_GET(MAX_HEADER_COUNT_CAP, regval); dev_dbg(&hci->master.dev, "%d DMA rings available\n", nr_rings); @@ -332,7 +319,7 @@ static int hci_dma_init(struct i3c_hci *hci) return -ENOMEM; hci->io_data = rings; rings->total = nr_rings; - rings->sysdev = sysdev; + rings->sysdev = i3c_hci_sysdev(hci->master.dev.parent); for (i = 0; i < rings->total; i++) { u32 offset = rhs_reg_read(RHn_OFFSET(i)); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h index b3d9803b1968..b8d2a3d680f8 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -184,6 +184,8 @@ void amd_set_resp_buf_thld(struct i3c_hci *hci); void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n); +struct device *i3c_hci_sysdev(struct device *dev); + #define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 int i3c_hci_rpm_suspend(struct device *dev); -- 2.53.0