From: sashiko-bot@kernel.org
To: "Gary Guo" <gary@garyguo.net>
Cc: "Alexandre Courbot" <acourbot@nvidia.com>,
linux-pci@vger.kernel.org, ojeda@kernel.org,
dri-devel@lists.freedesktop.org,
"Danilo Krummrich" <dakr@kernel.org>
Subject: Re: [PATCH v2 11/16] rust: io: register: support fixed offset register without bitfield
Date: Wed, 05 Aug 2026 16:50:42 +0000 [thread overview]
Message-ID: <20260805165043.0F7161F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260805-typed_register-v2-11-c3ca142220a0@garyguo.net>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `register!` macro documentation provides an example defining a FIFO register (`TX_FIFO`) with a `u32` type. This violates the subsystem guidelines which mandate that FIFOs must use stream accessors (no byteswapping). Using a `u32` register type implies standard register access (e.g., `writel`), which will byteswap on big-endian architectures and corrupt stream data. Additionally, the macro's syntax rule `$ty: ident $(:: $path_frag:ident)*` restricts the type to paths, preventing developers from directly specifying a byte array (e.g., `[u8; 4]`) as the type to properly model a byteswap-free stream.
--
--- Patch [11]: [PATCH v2 11/16] rust: io: register: support fixed offset register without bitfield ---
commit a13a899311e93c249f5925eff4ce304f82a4cb69
Author: Gary Guo <gary@garyguo.net>
rust: io: register: support fixed offset register without bitfield
Add a rule to allow creating `IoLoc` in `regiser!()` using an existing type
and not create a bitfield. Add an example to demonstrate this for FIFO
registers.
> diff --git a/rust/kernel/io/register.rs b/rust/kernel/io/register.rs
> index dc800fc711722..49a61da106c7d 100644
> --- a/rust/kernel/io/register.rs
> +++ b/rust/kernel/io/register.rs
[ ... ]
> @@ -499,6 +516,19 @@ fn into_io_op(self) -> (FixedRegisterLoc<T>, T) {
> /// In this example, `SCRATCH_BOOT_STATUS` uses the same I/O address as `SCRATCH`, while providing
> /// its own `completed` field.
> ///
> +/// If you do not wish to have a bitfield defined, you can also create a register using an existing
> +/// type.
> +///
> +/// ```no_run
> +/// # use kernel::io::*;
> +/// register! {
> +/// base: Region<0x1000>;
> +///
> +/// /// TX FIFO register.
> +/// pub TX_FIFO: u32 @ 0x00001000;
[Severity: Low]
Does this example promote an anti-pattern for FIFO access?
Using u32 for a FIFO implies standard register I/O accessors (like writel or
readl), which will perform byte-swapping on big-endian architectures.
According to the I/O accessor subsystem guidelines, FIFOs should use stream
accessors without byteswapping to prevent data corruption.
Would it be better to avoid using a FIFO as the example here, or use a type
that enforces stream semantics?
> +/// }
> +/// ```
> +///
> /// ## Relative registers
[ ... ]
> @@ -826,6 +856,23 @@ fn into_io_op(self) -> (FixedRegisterLoc<T>, T) {
> macro_rules! register {
> (base: $reg_base:ty;) => {};
>
> + // Creates a register at a fixed offset of the MMIO space with provided type.
> + (
> + base: $reg_base:ty;
> + // `$ty` cannot be `:ty` due to follow-set restrictions.
> + $(#[$attr:meta])* $vis:vis $name:ident: $ty: ident $(:: $path_frag:ident)*
[Severity: Low]
Does this macro rule prevent developers from specifying inline byte arrays
(like [u8; 4]) as the register type?
Since the type matcher is restricted to identifiers and paths, it seems
developers wouldn't be able to directly define a byte array to properly model
a byteswap-free stream without defining a separate type alias first.
Could this be adjusted to support array syntax, or is the limitation strict
enough to require type aliases for stream buffers?
> + $(@ $offset:literal)?
> + $(=> $alias:path $([$alias_idx:expr])? )?;
> + $($rest:tt)*
> + ) => {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260805-typed_register-v2-0-c3ca142220a0@garyguo.net?part=11
next prev parent reply other threads:[~2026-08-05 16:50 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-05 16:35 [PATCH v2 00/16] rust: io: support register projections and remove relative registers Gary Guo
2026-08-05 16:35 ` [PATCH v2 01/16] rust: io: add static `cast()` method for views Gary Guo
2026-08-05 16:50 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 02/16] rust: io: add `IoRepr` trait Gary Guo
2026-08-05 16:46 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 03/16] rust: io: support register projections Gary Guo
2026-08-05 16:42 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 04/16] rust: io: register: handle one register at a time Gary Guo
2026-08-05 16:43 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 05/16] rust: io: register extract offset computation to helper rules Gary Guo
2026-08-05 16:42 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 06/16] rust: io: register: allow explicit base type specification Gary Guo
2026-08-05 16:43 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 07/16] gpu: nova-core: specify base type for registers Gary Guo
2026-08-05 16:42 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 08/16] drm/tyr: " Gary Guo
2026-08-05 16:47 ` sashiko-bot
2026-08-05 16:59 ` Gary Guo
2026-08-05 16:35 ` [PATCH v2 09/16] samples: rust: pci: " Gary Guo
2026-08-05 16:41 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 10/16] rust: io: register: make register have a typed base Gary Guo
2026-08-05 16:43 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 11/16] rust: io: register: support fixed offset register without bitfield Gary Guo
2026-08-05 16:50 ` sashiko-bot [this message]
2026-08-05 17:05 ` Gary Guo
2026-08-05 16:35 ` [PATCH v2 12/16] gpu: nova-core: use projection for PFALCON and PFALCON2 registers Gary Guo
2026-08-05 16:46 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 13/16] gpu: nova-core: convert hshub0 from relative register to projection Gary Guo
2026-08-05 16:48 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 14/16] rust: io: register: remove relative registers Gary Guo
2026-08-05 16:51 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 15/16] rust: io: register: remove `Register` trait and cleanup macro Gary Guo
2026-08-05 16:48 ` sashiko-bot
2026-08-05 16:35 ` [PATCH v2 16/16] rust: io: register: unify handling of register with/without bitfields Gary Guo
2026-08-05 16:51 ` sashiko-bot
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