From: Yu Zhang <zhangyu1@linux.microsoft.com>
To: linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org,
iommu@lists.linux.dev, linux-pci@vger.kernel.org,
linux-arch@vger.kernel.org, x86@kernel.org
Cc: wei.liu@kernel.org, kys@microsoft.com, haiyangz@microsoft.com,
decui@microsoft.com, longli@microsoft.com, joro@8bytes.org,
will@kernel.org, robin.murphy@arm.com, bhelgaas@google.com,
kwilczynski@kernel.org, lpieralisi@kernel.org, mani@kernel.org,
robh@kernel.org, arnd@arndb.de, jgg@ziepe.ca,
mhklinux@outlook.com, jacob.pan@linux.microsoft.com,
tgopinath@linux.microsoft.com,
easwar.hariharan@linux.microsoft.com,
mrathor@linux.microsoft.com, baolu.lu@linux.intel.com,
suravee.suthikulpanit@amd.com, vasant.hegde@amd.com
Subject: [PATCH v3 3/5] iommu/x86: Share the architectural MSI reserved range
Date: Tue, 11 Aug 2026 23:50:19 +0800 [thread overview]
Message-ID: <20260811155022.108148-4-zhangyu1@linux.microsoft.com> (raw)
In-Reply-To: <20260811155022.108148-1-zhangyu1@linux.microsoft.com>
Intel and AMD IOMMU drivers both reserve the x86 architectural MSI
address window from normal IOVA mappings. Define the range in the
common x86 IOMMU header and use it in both drivers.
Signed-off-by: Yu Zhang <zhangyu1@linux.microsoft.com>
---
arch/x86/include/asm/iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 7 +++----
drivers/iommu/intel/iommu.c | 7 +++----
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index 3be2451e7bc8..386db10ea909 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -6,6 +6,9 @@
#include <asm/e820/api.h>
+#define X86_IOMMU_MSI_RANGE_START 0xfee00000
+#define X86_IOMMU_MSI_RANGE_END 0xfeefffff
+
extern int force_iommu, no_iommu;
extern int iommu_detected;
extern int iommu_merge;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 29dc18d3d22e..ead96acdb766 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -50,8 +50,6 @@
#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
/* Reserved IOVA ranges */
-#define MSI_RANGE_START (0xfee00000)
-#define MSI_RANGE_END (0xfeefffff)
#define HT_RANGE_START (0xfd00000000ULL)
#define HT_RANGE_END (0xffffffffffULL)
@@ -3097,8 +3095,9 @@ static void amd_iommu_get_resv_regions(struct device *dev,
list_add_tail(®ion->list, head);
}
- region = iommu_alloc_resv_region(MSI_RANGE_START,
- MSI_RANGE_END - MSI_RANGE_START + 1,
+ region = iommu_alloc_resv_region(X86_IOMMU_MSI_RANGE_START,
+ X86_IOMMU_MSI_RANGE_END -
+ X86_IOMMU_MSI_RANGE_START + 1,
0, IOMMU_RESV_MSI, GFP_KERNEL);
if (!region)
return;
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 849d06dfe1ae..500f6fa5bf72 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -39,8 +39,6 @@
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
-#define IOAPIC_RANGE_START (0xfee00000)
-#define IOAPIC_RANGE_END (0xfeefffff)
#define IOVA_START_ADDR (0x1000)
#define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
@@ -3432,8 +3430,9 @@ static void intel_iommu_get_resv_regions(struct device *device,
}
#endif /* CONFIG_INTEL_IOMMU_FLOPPY_WA */
- reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,
- IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,
+ reg = iommu_alloc_resv_region(X86_IOMMU_MSI_RANGE_START,
+ X86_IOMMU_MSI_RANGE_END -
+ X86_IOMMU_MSI_RANGE_START + 1,
0, IOMMU_RESV_MSI, GFP_KERNEL);
if (!reg)
return;
--
2.52.0
next prev parent reply other threads:[~2026-08-11 15:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 15:50 [PATCH v3 0/5] Hyper-V: Add para-virtualized IOMMU support for Linux guests Yu Zhang
2026-08-11 15:50 ` [PATCH v3 1/5] hyperv: Introduce new hypercall interfaces used by Hyper-V guest IOMMU Yu Zhang
2026-08-11 15:50 ` [PATCH v3 2/5] Drivers: hv: Add logical device ID registry for vPCI devices Yu Zhang
2026-08-11 15:50 ` Yu Zhang [this message]
2026-08-11 16:21 ` [PATCH v3 3/5] iommu/x86: Share the architectural MSI reserved range Jason Gunthorpe
2026-08-11 15:50 ` [PATCH v3 4/5] iommu/hyperv: Add para-virtualized IOMMU support for Hyper-V guest Yu Zhang
2026-08-11 15:50 ` [PATCH v3 5/5] iommu/hyperv: Add page-selective IOTLB flush support Yu Zhang
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