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Wed, 19 Aug 2026 01:37:00 -0700 Date: Wed, 19 Aug 2026 11:36:58 +0300 From: Zhi Wang To: Danilo Krummrich CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v7 1/1] rust: pci: add extended capability and SR-IOV support Message-ID: <20260819113658.4d096da5@inno-dell> In-Reply-To: References: <20260804161612.776752-1-zhiw@nvidia.com> <20260804161612.776752-2-zhiw@nvidia.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006003:EE_|MW3PR12MB4362:EE_ X-MS-Office365-Filtering-Correlation-Id: 41051835-3d66-4448-f67e-08defdcd15b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|7416014|36860700016|1800799024|82310400026|22082099003|18002099003|56012099006|6133799003|10067099003|11063799006|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /kFKkgT5ise8f1TuoGS8ezGY2NsNDauWFvP+N6iFykiSoJtYqN8sbozlczsFrPTPQGAkWians3qOQts0BkcGYXYsTqmi/hl+CzNFpwSAqiNDVuY4iVq083SL6BKtMj491uWeeJFkhnFIgtJfqFkOLb6fFZJFiZmKvmKVRoqoIKB/hcTMq6q2p7s7Vr/+HigNUNX2JX022ru9YT5qHjqX8u1fnxSG8pNjumC/2+qRe4URMnaQCqSd1ra1sbeskYnJEff4hxVfWP81hFobPT1pM0zW6HklBoLdIFAkeEKRZPg+lT9K2BgbMhIKv62o+YWfvYivVuZrvenexvk/5oB0nT0KIj88Hu1KnFZrS1tG/9UNkxi/hG2A4kZdN+f7bVKDlHK0IXgwINQgrIkqtS9kbqgIUQJJjIgJbfHzVMS2DTuFujcnbvZV8TgYcIQM4Cao X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2026 08:37:20.5416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41051835-3d66-4448-f67e-08defdcd15b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006003.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4362 On Thu, 13 Aug 2026 15:56:41 +0200 "Danilo Krummrich" wrote: Hi Danilo: I have updated the v8 to address all the comments except the io projection part. Regarding to Gary's new Io project patch, I would send another re-spin after they are on drm-rust-next. Thanks for the review. Z. > On Tue Aug 4, 2026 at 6:16 PM CEST, Zhi Wang wrote: > > +/// Number of VF BAR register slots in an SR-IOV capability. > > +// CAST: `PCI_SRIOV_NUM_BARS` is 6, which fits in `usize`. >=20 > I think the more relevant point is that it is a constant coming from > the PCIe spec. (Plus, more SR-IOV BARs than addressable bytes > wouldn't make a lot of sense anyway. :) >=20 > > +const NUM_VF_BARS: usize =3D bindings::PCI_SRIOV_NUM_BARS as usize; > > + > > +/// PCI extended capability IDs. > > +#[repr(u16)] > > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > > +pub enum ExtCapId { > > + /// Single Root I/O Virtualization. > > + // CAST: `PCI_EXT_CAP_ID_SRIOV` is `0x10`, which fits in `u16`. >=20 > Same here, I'd mention that it is a constant from the spec. >=20 > > + Sriov =3D bindings::PCI_EXT_CAP_ID_SRIOV as u16, > > +} >=20 > [...] >=20 > > +impl<'a> ConfigSpace<'a, Extended> { > > + /// Finds and projects an extended capability into its typed > > register layout. > > + /// > > + /// Returns [`None`] if the device does not implement the > > capability. > > + /// > > + /// # Examples > > + /// > > + /// ```no_run > > + /// use kernel::pci; > > + /// > > + /// fn probe_sriov( > > + /// pdev: &pci::Device, > > + /// ) -> Result<(), kernel::error::Error> { >=20 > Just Result; please also import kernel::device::Bound for readability. >=20 > io_read!() should be imported from kernel::io::. >=20 > > +/// SR-IOV register layout per PCIe spec (64 bytes starting at cap > > offset). +#[repr(C)] > > +#[derive(FromBytes, IntoBytes)] > > +pub struct ExtSriovRegs { > > + /// Extended capability header. > > + pub header: u32, > > + /// SR-IOV capabilities. > > + pub cap: u32, > > + /// SR-IOV control. > > + pub ctrl: u16, > > + /// SR-IOV status. > > + pub status: u16, >=20 > This is not a raw value, but a bitfield and should be represented as > such (might be true for some other fields as well). >=20 > I think for this to work it needs Gary's recent I/O series though; I > can merge both together next cycle and share with drm-rust. >=20 > > + /// Initial VFs. > > + pub initial_vfs: u16, > > + /// Total VFs. > > + pub total_vfs: u16, > > + /// Number of VFs. > > + pub num_vfs: u16, > > + /// Function dependency link. > > + pub func_dep_link: u8, > > + _reserved_0: u8, > > + /// First VF offset. > > + pub vf_offset: u16, > > + /// VF stride. > > + pub vf_stride: u16, > > + _reserved_1: u16, > > + /// VF device ID. > > + pub vf_device_id: u16, > > + /// Supported page sizes. > > + pub supported_page_sizes: u32, > > + /// System page size. > > + pub system_page_size: u32, > > + /// VF BARs (BAR0=E2=80=93BAR5). > > + pub vf_bar: [u32; NUM_VF_BARS], > > + /// VF migration state array offset. > > + pub migration_state: u32, > > +}