Re: [PATCH] pci: designware: Set DMA_BYPASS bit in outbound IATU CTRL2 register

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unconditionally setting PCIE_ATU_DMA_BYPASS on all outbound iATU windows breaks built-in eDMA for platforms relying on iATU translation.
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commit 0264996407d5cc39725b0bb26bca8b42a6f11d18
Author: Sumit Kumar <sumit.kumar@oss.qualcomm.com>

pci: designware: Set DMA_BYPASS bit in outbound IATU CTRL2 register

This commit unconditionally sets the DMA_BYPASS bit in PCIE_ATU_REGION_CTRL2
when programming outbound iATU regions for controllers >= 4.60A. This aims
to prevent unintentional address translation when DMA destination addresses
fall within an outbound iATU aperture.

> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 593388f29bdd4..9297d0e607e3a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -577,6 +577,8 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>  		/* The data-less messages only for now */
>  		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
>  	}
> +	if (dw_pcie_ver_is_ge(pci, 460A))
> +		val |= PCIE_ATU_DMA_BYPASS;
>  	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);

[Severity: High]
Does unconditionally setting PCIE_ATU_DMA_BYPASS on all outbound iATU
windows break built-in eDMA for platforms that rely on iATU translation?

When a standard PCI endpoint function driver allocates an outbound memory
window using pci_epc_mem_map(), it gets a local CPU physical address which
is then programmed into the DMA engine.

Because this patch unconditionally bypasses the iATU for DMA, these
platforms will send the raw CPU physical address over the PCIe link instead
of the intended PCIe bus address. Could this regression lead to host memory
corruption, IOMMU faults, or silent data corruption on platforms where the
eDMA expects the iATU to handle the CPU-to-PCI address translation?

To support bypassing safely, would this need to be conditionally enabled via
a platform quirk, or require implementing the .pci_address callback in
dw_pcie_edma_ops to translate the CPU address in software before programming
the eDMA channel?

>  
>  	/*

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Sashiko AI review · https://sashiko.dev/#/patchset/20260826-dma_bypass-v1-1-3a53dc748ce2@oss.qualcomm.com?part=1