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Wed, 26 Aug 2026 11:53:54 -0700 Date: Wed, 26 Aug 2026 21:53:51 +0300 From: Zhi Wang To: Danilo Krummrich CC: Alexandre Courbot , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v8 1/1] rust: pci: add extended capability and SR-IOV support Message-ID: <20260826215351.07940b1d@inno-dell> In-Reply-To: References: <20260818084633.1673214-1-zhiw@nvidia.com> <20260818084633.1673214-2-zhiw@nvidia.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002327:EE_|SA3PR12MB8812:EE_ X-MS-Office365-Filtering-Correlation-Id: 2993d201-0631-4e55-ee7c-08df03a37054 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700016|1800799024|23010399003|13003099007|6133799003|56012099006|10067099003|5023799004|11063799006|4143699003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2eoiBLR1f9LXpXvnxP9VwwTP2HoeHYpuDR1Pb6Wo9rzo8OMFFhbsyLNusuyEyY1qmbI6LcqXXl5bAYld0fH838mf1X179VN584vgD76iYLkZ/ExQA7up5pE28Tai3ajXcjynyHoC9Lp+IVoEXfTahHWQ0L5zClYsnCSWZwMFejuTM4669eobSLpcs1mdbUwVSyauedMlmNtPcBQVpLLDS8yOocPSE0xIML0u7LKCyx2UrBIlMRYfunGMmHg5Nu9To/Q7Zl5aUAzEzgCmk2iyGWayv/bccrSdfyUXBK2LvZaoFiR5EkbkQE7uZLcNT7RJEi/zY2xJcrwp9JRqHCLbEn0X1pqcXiW5JYGwHfwWjtP/DtAw3HmUkWpsMe7YNpVLUmmRdQySk/UUMv/qf1a7iNKRO+qYlBaNJmYca8P356mhZDsmh5Uge160gys/uAQV X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2026 18:54:20.8894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2993d201-0631-4e55-ee7c-08df03a37054 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002327.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8812 On Mon, 24 Aug 2026 13:38:05 +0200 "Danilo Krummrich" wrote: > On Mon Aug 24, 2026 at 10:12 AM CEST, Alexandre Courbot wrote: snip. > >> +/// SR-IOV register layout per PCIe spec (64 bytes starting at > >> cap offset). +#[repr(C)] > >> +#[derive(FromBytes, IntoBytes)] > >> +pub struct ExtSriovRegs { > >> + /// Extended capability header. > >> + _header: u32, > >> + /// SR-IOV capabilities. > >> + pub cap: u32, > >> + /// SR-IOV control. > >> + pub ctrl: u16, =20 >=20 > Why is this public? >=20 This is identical to register definition layout in the PCI spec. And it is a straight-forward idea. Do we prefer to: a. keep the complete register definition layout here, while only expose the ones that allow the user to access. or b. only keep the allowlist of registers in a enum(offset)? > >> + /// SR-IOV status. > >> + pub status: u16, =20 >=20 > Why do drivers need to read this directly? >=20 > >> + /// Initial VFs. > >> + pub initial_vfs: u16, > >> + /// Total VFs. > >> + pub total_vfs: u16, > >> + /// Number of VFs. > >> + pub num_vfs: u16, =20 >=20 > Why do we need to mess with this? This should only ever be written > through pci_enable_sriov()? >=20 > >> + /// Function dependency link. > >> + pub func_dep_link: u8, > >> + _reserved_0: u8, > >> + /// First VF offset. > >> + pub vf_offset: u16, > >> + /// VF stride. > >> + pub vf_stride: u16, =20 >=20 > Those two are read by the PCI core in pci_iov_set_numvfs() and uses > them internally. Why do we need a driver API for those? >=20 > Why can't we use pci_iov_virtfn_devfn()? >=20 GSP VF_INFO requires the first VF offset to be filled [1], it requires the raw value from the registers instead of the calculated one in pci_iov_virtfn_devfn(). [1] https://lore.kernel.org/all/20260804170045.902069-2-zhiw@nvidia.com/ > >> + _reserved_1: u16, > >> + /// VF device ID. > >> + pub vf_device_id: u16, > >> + /// Supported page sizes. > >> + pub supported_page_sizes: u32, > >> + /// System page size. > >> + pub system_page_size: u32, =20 >=20 > Isn't this already taken care of by the PCI core? Do we need to > expose this? >=20 > >> + /// VF BARs (BAR0=E2=80=93BAR5). > >> + pub vf_bar: [u32; NUM_VF_BARS], =20 > > > > Now that we have an iterator method, we can make this member > > private. I'd even say we should as making this public enables the > > kinds of invalid accesses we built the iterator to avoid. =20 >=20 > Agreed. >=20 > >> + /// VF migration state array offset. > >> + pub migration_state: u32, =20 >=20 > Do we need this? Isn't this obsolete? >=20 > > pub fn vf_bars(&self) -> Result > ExtSriovVfBar>> { let slots: [u32; NUM_VF_BARS] =3D > > core::array::from_fn(|slot| crate::io_read!(*self, > > .vf_bar[panic: slot])); let mut slots =3D slots.into_iter(); > > let mut bars =3D [None; NUM_VF_BARS]; > > let mut count =3D 0; > > > > while let Some(low) =3D slots.next().map(VfBarLow::from) { > > if low.io_space() { > > return Err(EINVAL); > > } > > > > let low_address =3D u64::from(low.address()) << > > VfBarLow::ADDRESS_SHIFT; let bar =3D match low.memory_type()? { > > VfBarMemoryType::Bits64 =3D> ExtSriovVfBar { > > address: > > (u64::from(slots.next().ok_or(EINVAL)?) << 32) | low_address, > > is_64bit: true, }, > > VfBarMemoryType::Bits32 =3D> ExtSriovVfBar { > > address: low_address, > > is_64bit: false, > > }, > > }; > > > > bars[count] =3D Some(bar); > > count +=3D 1; > > } > > > > Ok(bars.into_iter().flatten()) > > } > > > > With this you don't need `ExtSriovVfBars` at all, which removes a > > bit (almost 50 LoCs!) of code. =20 >=20 > LGTM, thanks for improving this.