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From: sashiko-bot@kernel.org
To: "Nicolin Chen" <nicolinc@nvidia.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 07/13] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU
Date: Tue, 01 Sep 2026 00:55:58 +0000	[thread overview]
Message-ID: <20260901005559.450671F000E9@smtp.kernel.org> (raw)
In-Reply-To: <a6fba7f7a01f5955dfb44d34adc6262c8534e829.1788222486.git.nicolinc@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The system shutdown path disables the SMMU without quiescing queue IRQs, leading to an infinite loop in the kernel thread.
--

commit 723b797a0d5bc30d8469f53716a51e3b4d1bb03c
Author: Nicolin Chen <nicolinc@nvidia.com>

iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU

This commit addresses an issue where disabling the SMMU while queue IRQs are
running leads to commands being issued to a queue consuming nothing. It
ensures that the queue IRQ threads are quiesced by disabling the IRQs before
the SMMU is disabled in device reset and disable action paths.

> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 64540cfb73244..d45d97f356cf0 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
[ ... ]
> @@ -4992,10 +5001,22 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
>  	return ret;
>  }
>  
> +/* Quiesce the queue IRQ threads, e.g. before disabling the SMMU */
> +static void arm_smmu_disable_irqs(struct arm_smmu_device *smmu)
> +{
> +	if (smmu->combined_irq)
> +		disable_irq(smmu->combined_irq);
> +	if (smmu->evtq.q.irq)
> +		disable_irq(smmu->evtq.q.irq);
> +	if (smmu->priq.q.irq)
> +		disable_irq(smmu->priq.q.irq);
> +}
> +
>  static void arm_smmu_disable_action(void *data)
>  {
>  	struct arm_smmu_device *smmu = data;
>  
> +	arm_smmu_disable_irqs(smmu);

[Severity: High]
This is a pre-existing issue, but since this patch explicitly aims to fix
the vulnerability where the SMMU is disabled without quiescing the IRQs,
does the system shutdown path also need to be updated to call
arm_smmu_disable_irqs()?

Looking at arm_smmu_device_shutdown() which is called during system shutdown:

static void arm_smmu_device_shutdown(struct platform_device *pdev)
{
	struct arm_smmu_device *smmu = platform_get_drvdata(pdev);

	arm_smmu_device_disable(smmu);
}

The shutdown path directly disables the SMMU without first quiescing the
threaded IRQs. Because devm callbacks do not run on shutdown, the IRQ handlers
remain active while the hardware is disabled.

If a pending PRIQ or EVTQ event triggers, the threaded handler
(e.g., arm_smmu_priq_thread) executes and calls arm_smmu_page_response(),
which attempts to insert a PRI_RESP command into the CMDQ without waiting for
a SYNC. Since the SMMU is hardware-disabled, it will not process commands and
the CMDQ software ring buffer quickly fills up. Once full,
__arm_smmu_cmdq_issue_cmdlist() enters a while (!queue_has_space(...)) loop
which either spins tightly or times out every second, looping indefinitely
without any breakout condition.

Could we also add a call to arm_smmu_disable_irqs(smmu) in
arm_smmu_device_shutdown() to prevent this infinite loop?

>  	if (smmu->impl_ops && smmu->impl_ops->device_disable)
>  		smmu->impl_ops->device_disable(smmu);
>  	arm_smmu_device_disable(smmu);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1788222485.git.nicolinc@nvidia.com?part=7

  reply	other threads:[~2026-09-01  0:55 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-01  0:33 [PATCH v3 00/13] iommu/arm-smmu-v3: Add PRI support Nicolin Chen
2026-09-01  0:33 ` [PATCH v3 01/13] iommu/arm-smmu-v3: Add arm_smmu_attach_release() Nicolin Chen
2026-09-01  0:46   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 02/13] iommu/arm-smmu-v3: Add Q_POS() macro Nicolin Chen
2026-09-01  0:38   ` sashiko-bot
2026-09-01  0:33 ` [PATCH v3 03/13] iommu/arm-smmu-v3: Drain in-flight fault events on domain detach Nicolin Chen
2026-09-01  0:48   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 04/13] iommu/arm-smmu-v3: Flush in-flight fault work " Nicolin Chen
2026-09-01  0:55   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 05/13] iommu/arm-smmu-v3: Allocate IOPF queue without FEAT_SVA Nicolin Chen
2026-09-01  0:46   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 06/13] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Nicolin Chen
2026-09-01  0:53   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 07/13] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU Nicolin Chen
2026-09-01  0:55   ` sashiko-bot [this message]
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 08/13] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Nicolin Chen
2026-09-01  0:47   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 09/13] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Nicolin Chen
2026-09-01  0:50   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 10/13] iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI Nicolin Chen
2026-09-01  0:43   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 11/13] PCI/ATS: Add PRI stubs Nicolin Chen
2026-09-01  0:42   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 12/13] PCI/ATS: Export pci_enable_pri() and pci_reset_pri() Nicolin Chen
2026-09-01  0:44   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-01  0:33 ` [PATCH v3 13/13] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Nicolin Chen
2026-09-01  0:51   ` sashiko-bot
2026-09-03 19:18   ` Jonathan Cameron
2026-09-03 19:18 ` [PATCH v3 00/13] iommu/arm-smmu-v3: Add PRI support Jonathan Cameron

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