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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF00000148.mail.protection.outlook.com (10.167.244.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Tue, 1 Sep 2026 09:34:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 1 Sep 2026 02:34:19 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 1 Sep 2026 02:34:16 -0700 From: Shameer Kolothum To: , , CC: , , , , , , , , Subject: [RFC PATCH 17/19] vfio/pci: Add generic PCI error resume handling Date: Tue, 1 Sep 2026 10:32:15 +0100 Message-ID: <20260901093217.8539-18-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901093217.8539-1-skolothumtho@nvidia.com> References: <20260901093217.8539-1-skolothumtho@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|DS7PR12MB6215:EE_ X-MS-Office365-Filtering-Correlation-Id: d5ddda40-c5a5-481d-4812-08df080c3cdf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|23010399003|10067099003|56012099006|11063799006|22082099003|18002099003; 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It ends the recovery transaction and makes the device usable again. INTX_DISABLE is taken from the INTx state rather than from the saved word. The handler can have masked the line after the word was saved, and restoring the saved bit would unmask a line it still believes is masked. The replay is what unmasks it. Restore the command word saved by error_detected(), unless the device was reset, in which case slot_reset() already restored the whole config space and the saved value is stale. Then unblock access, un-revoke exported DMA-BUFs if the guest still has memory decode enabled, clear IN_PROGRESS and replay the INTx state recorded during the event. If the command write fails, keep access blocked and publish FAILED. IN_PROGRESS is cleared and FAILED set in a single store, so a lock-free reader never sees the intermediate state, which would read as a successful completion. Pay any deferred ROM decode disable first, before the in-progress check. A failed transaction has already cleared that flag, and the disable would be lost. The helper skips a closed device on its own. Until a later patch starts a recovery transaction, only the deferred ROM disable runs here. The rest returns early. Signed-off-by: Shameer Kolothum --- drivers/vfio/pci/vfio_pci_core.c | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 658cccecab12..eed0430c32ee 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -2828,6 +2828,73 @@ static pci_ers_result_t vfio_pci_core_aer_slot_reset(struct pci_dev *pdev) return result; } +static void vfio_pci_core_aer_resume(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *vdev = dev_get_drvdata(&pdev->dev); + unsigned long irq_flags; + u32 flags; + int ret = 0; + + down_write(&vdev->recovery_lock); + + /* + * Pay any deferred ROM disable before the in-progress check below, + * which a failed transaction has already cleared, or it would be + * lost. + */ + vfio_pci_recovery_rom_disable(vdev); + + if (!(vdev->pci_recovery_flags & VFIO_PCI_RECOVERY_IN_PROGRESS)) + goto out_unlock; + + if (!vdev->pci_recovery_device_open) { + vdev->pci_recovery_command_valid = false; + WRITE_ONCE(vdev->pci_recovery_flags, + vdev->pci_recovery_flags & + ~VFIO_PCI_RECOVERY_IN_PROGRESS); + goto out_unlock; + } + + down_write(&vdev->memory_lock); + /* + * Restore the command word and clear access_blocked under irqlock. + * The INTx handler writes the same register through + * pci_check_and_mask_intx(), so it must not interleave with the + * restore, and it must not see access blocked cleared while the + * temporary command value is still installed. + * + * INTX_DISABLE comes from the INTx state rather than from the saved + * word, which can be older than the last mask. The replay below is + * what unmasks the line. + */ + spin_lock_irqsave(&vdev->irqlock, irq_flags); + if (!(vdev->pci_recovery_flags & VFIO_PCI_RECOVERY_RESET) && + vdev->pci_recovery_command_valid) { + u16 cmd = vdev->pci_recovery_command; + + cmd = vfio_pci_intx_recovery_command(vdev, cmd); + ret = pci_write_config_word(pdev, PCI_COMMAND, cmd); + } + if (!ret) + WRITE_ONCE(vdev->pci_recovery_access_blocked, false); + spin_unlock_irqrestore(&vdev->irqlock, irq_flags); + if (!ret && __vfio_pci_memory_enabled(vdev)) + vfio_pci_dma_buf_move(vdev, false); + up_write(&vdev->memory_lock); + + vdev->pci_recovery_command_valid = false; + flags = vdev->pci_recovery_flags & ~VFIO_PCI_RECOVERY_IN_PROGRESS; + if (ret) + flags |= VFIO_PCI_RECOVERY_FAILED; + WRITE_ONCE(vdev->pci_recovery_flags, flags); + if (!ret) + vfio_pci_intx_recovery_finish(vdev); + +out_unlock: + up_write(&vdev->recovery_lock); + wake_up_all(&vdev->pci_recovery_wait); +} + int vfio_pci_core_sriov_configure(struct vfio_pci_core_device *vdev, int nr_virtfn) { @@ -2901,6 +2968,7 @@ EXPORT_SYMBOL_GPL(vfio_pci_core_sriov_configure); const struct pci_error_handlers vfio_pci_core_err_handlers = { .error_detected = vfio_pci_core_aer_err_detected, .slot_reset = vfio_pci_core_aer_slot_reset, + .resume = vfio_pci_core_aer_resume, }; EXPORT_SYMBOL_GPL(vfio_pci_core_err_handlers); -- 2.43.0