From: Bjorn Helgaas <helgaas@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: jingoohan1@gmail.com, bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
a-garg7@ti.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Feizhou Yu <yufeizhou201@163.com>
Subject: Re: [PATCH] pci: dwc: Rename PCIE_PORT_LINK_CONTROL to PORT_LINK_CTRL_OFF
Date: Fri, 4 Sep 2026 12:13:25 -0500 [thread overview]
Message-ID: <20260904171325.GA2326692@bhelgaas> (raw)
In-Reply-To: <7eb29846-7561-4ead-9a05-0c5966de5fd6@163.com>
On Sat, Sep 05, 2026 at 12:32:30AM +0800, Hans Zhang wrote:
> On 9/5/26 00:12, Bjorn Helgaas wrote:
> > On Fri, Sep 04, 2026 at 02:18:23PM +0800, Hans Zhang wrote:
> > > The register at offset 0x710 is documented in the Synopsys DesignWare
> > > PCIe Controller Reference Manual as "PORT_LINK_CTRL_OFF" (Port Link
> > > Control Register). The current macro name PCIE_PORT_LINK_CONTROL does
> > > not match the documentation, making it difficult to cross-reference
> > > with the spec when debugging or maintaining the code.
> ...
> I agree with what you said. The official documentation of Synopsys currently
> defines it this way. If the naming is simplified, it would make it harder to
> search for where the registers are located. This is one of the purposes of
> this modification.
One possibility is to add a one-line comment at the #define containing
the name used in the spec. It's not perfect, but that's basically
what's in pci_regs.h:
#define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
#define PCI_EXP_LNKCTL 0x10 /* Link Control */
#define PCI_EXP_LNKSTA 0x12 /* Link Status */
prev parent reply other threads:[~2026-09-04 17:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 6:18 [PATCH] pci: dwc: Rename PCIE_PORT_LINK_CONTROL to PORT_LINK_CTRL_OFF Hans Zhang
2026-09-04 6:24 ` sashiko-bot
2026-09-04 16:12 ` Bjorn Helgaas
2026-09-04 16:32 ` Hans Zhang
2026-09-04 17:13 ` Bjorn Helgaas [this message]
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