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From: sashiko-bot@kernel.org
To: "Mario Limonciello" <mario.limonciello@amd.com>
Cc: cassel@kernel.org, linux-ide@vger.kernel.org, dlemoal@kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports
Date: Tue, 08 Sep 2026 17:14:27 +0000	[thread overview]
Message-ID: <20260908171427.A111A1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260908170035.160166-2-mario.limonciello@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] Hardware state loss across suspend/resume causing data corruption
--

commit 6c1c185449d3f44e1db8d42c0f5b1f2a64c2eeb8
Author: Mario Limonciello <mario.limonciello@amd.com>

x86/PCI: Disable enhanced atomics on some AMD PCIe ports

This commit disables enhanced atomic operations on PCIe ports for AMD
NBIO 7.7 and 7.11 based models to prevent data corruption with 64-bit DMA.
The issue occurs when the 32-bit IOVA space is exhausted on certain BIOSes.

Closes: https://lore.kernel.org/all/178789300872.392066.15963676631650361573@gmail.com/
Closes: https://lore.kernel.org/linux-ide/20260406222335.379935-1-artmoty@gmail.com/
Closes: https://lore.kernel.org/linux-ide/20260621100844.1224301-1-alvinwylim@gmail.com/

> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index b301c6c8df753..0857fd9365ec2 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c

[ ... ]

> +/* Phoenix, Hawk Point (NBIO 7.7) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x14E8,
> +			quirk_amd_nbio_7_7_disable_enhanced_atomic);
> +
> +/* Strix, Krackan, Strix Halo (NBIO 7.11) */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1507,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1122,
> +			quirk_amd_nbio_7_11_disable_enhanced_atomic);

[Severity: Critical]
Is this fixup lost across suspend and resume cycles?

Because the quirk is only registered for the final boot phase using
DECLARE_PCI_FIXUP_FINAL, the PCI core will not re-apply it during system
wake (which relies on DECLARE_PCI_FIXUP_RESUME).

If the system suspends to S3 or s2idle, the NBIO power domain is gated and
SMN registers lose their state. When the system resumes, the firmware
re-initializes these SMN registers to their default state (which has
enhanced atomics enabled). 

Because the kernel does not re-apply the quirk on resume, any subsequent
64-bit DMA traffic after waking from sleep could trigger the data
corruption this code is intended to prevent. 

Should these quirks also be registered with DECLARE_PCI_FIXUP_RESUME?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908170035.160166-1-mario.limonciello@amd.com?part=1

  reply	other threads:[~2026-09-08 17:14 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08 17:00 [PATCH 0/2] Fix for storage corruption w/ AMD IOMMU on 64-bit DMA Mario Limonciello
2026-09-08 17:00 ` [PATCH 1/2] x86/PCI: Disable enhanced atomics on some AMD PCIe ports Mario Limonciello
2026-09-08 17:14   ` sashiko-bot [this message]
2026-09-08 17:25     ` Mario Limonciello
2026-09-08 19:18   ` Bjorn Helgaas
2026-09-08 19:19     ` Mario Limonciello
2026-09-08 17:00 ` [PATCH 2/2] Revert "ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585" Mario Limonciello
2026-09-08 17:06   ` sashiko-bot

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