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charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=M+997Sws c=1 sm=1 tr=0 ts=6aa19d55 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=aNnz9XPx1a4JIXSYt2cE/A==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=Ikd4Dj_1AAAA:8 a=9koHXFDKl-DiS4GoSb4A:9 a=CjuIK1q_8ugA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: IScpRgEKSKkXBgaOGzcnjPYhacE_LAHe X-Proofpoint-ORIG-GUID: IScpRgEKSKkXBgaOGzcnjPYhacE_LAHe X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDE5OSBTYWx0ZWRfX/ZquwoFzJxzP MrFF0aIEcQYArbLf8jbzl2Q/Kl48djmhC7pDWuRwyPZmWtjG40SZEj5inLJ4Lw7m+B0GYwG91aO xqbliZEbcAg1OP9XDYb4wUQUfpjVPtg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDE5OSBTYWx0ZWRfX2+3UPMEx9ONt zUUAgDL2Oef6v7vrW5YBIcM3wVWRRJ1POwnhOyg4ldWmp9JbqwrXqB6JLjG+gXxXhDKNGda0pBd 37VyJ4q+YBLMIrHlg3dEygR0vTxZCQ/K2CCU7zs+MRlRHLSjvEyR6olM4HwwQy4FMI0BONaQKgQ sCAevGdhtKMPpjuk75IcbIkppmHnrdI4ucDQ2r0GUzEL1Gf5JDUXfJkTMd7pXnAUogb/Et8E+Va 93ZmI4G4K64XZWdPsqSrG3/wlnc7iJ9q9gaNQeivQwoIgQmaRn5YOAoPLzkQEo/Zw2ZPKtLibG/ FPsaBgcipr8pmSRDXQ5qKvZEx6pzR+Fup6cquj0bGuKnxc1NXI9uKXWEI5IifgpabYyJBK+OtVO hEqg0aEQkkx1645q/IzwZO06GWavnyQ2nR5FgPft6gOkm5iZUtbSxgS1D/d9BYL4T8+bkSwqbjs Lb3yCwDiC9EJOL+/mgg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090199 On Fri, 4 Sep 2026 18:15:37 -0700 Nicolin Chen wrote: > On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > > To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() > > > must issue a CMDQ_OP_PRI_RESP back to the SMMU. > > > > > > A stall event in the EVTQ and a PRI request in the PRIQ both surface to the > > > IOPF infrastructure with fault.type == IOMMU_FAULT_PAGE_REQ. SMMUv3 forbids > > > the Stall model on PCIe streams (PCIe must use Terminate), and PRI is only > > > > There are those systems that annoy some because they smell like PCIe > > (present PCIe software interfaces) but aren't and use stall mode. However, it > > is nonsense to use PRI with stall mode. So, instead I'd just argue that for > > stall the fault handling is done synchronously from a device point of > > view so a PRI request makes no sense rather htan associating this with > > PCIe as such. > > I changed the paragraph to: > > A stall event in the EVTQ and a PRI request in the PRIQ both surface to the > IOPF infrastructure with fault.type == IOMMU_FAULT_PAGE_REQ. Yet, both two > models are alternatives: a stalling master resolves a fault synchronously, > holding the transaction until a CMDQ_OP_RESUME, so it has no reason to also > issue a page request. A later change refuses PRI on a stall_enabled master, > so the two will never co-occur. arm_smmu_page_response() can therefore key > on the master state: CMDQ_OP_RESUME for stall_enabled, CMDQ_OP_PRI_RESP for > pri_enabled, mapping IOMMU_PAGE_RESP_* to the PRI response codes. > Nice.