From: sashiko-bot@kernel.org
To: "Ard Biesheuvel" <ardb+git@google.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [RFC PATCH] PCI: Tolerate non-prefetchable 64-bit BARs in prefetchable windows
Date: Thu, 10 Sep 2026 14:42:38 +0000 [thread overview]
Message-ID: <20260910144239.334761F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260910143440.3865663-2-ardb+git@google.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect Bridge Prefetching Check: The condition uses the child device's PCIe capability to infer bus prefetching behavior, allowing unsafe speculative reads on conventional PCI buses.
--
commit c6de2abeab7f85fbfb09d4554945da6aa13b56ac
Author: Ard Biesheuvel <ardb@kernel.org>
PCI: Tolerate non-prefetchable 64-bit BARs in prefetchable windows
This commit updates the PCI core to tolerate firmware allocations of
non-prefetchable 64-bit BARs inside prefetchable bridge windows for PCIe
devices. It bypasses the previous rejection logic by explicitly checking
the device's PCIe capability.
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b2879a6be5f80..e33eb9f3a1394 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -761,7 +761,8 @@ struct resource *pci_find_parent_resource(const struct pci_dev *dev,
> * not, the allocator made a mistake.
> */
> if (r->flags & IORESOURCE_PREFETCH &&
> - !(res->flags & IORESOURCE_PREFETCH))
> + !(res->flags & IORESOURCE_PREFETCH) &&
> + !pci_is_pcie(dev))
[Severity: High]
Could this logic mistakenly expose devices on conventional PCI buses to
unsafe speculative reads?
If a system has a PCI-to-PCIe reverse bridge connected to a conventional
PCI bus, the reverse bridge is the child device and has a PCIe capability.
In this scenario, wouldn't pci_is_pcie(dev) evaluate to true in
pci_find_parent_resource?
If firmware maps a non-prefetchable resource of this reverse bridge into a
prefetchable window of the upstream conventional PCI bridge, this check
would allow the kernel to successfully claim it.
When the CPU reads from this range, the upstream conventional PCI bridge
will issue speculative burst reads on the conventional PCI bus.
Could this cause unintended read side-effects like advancing FIFOs or clearing
read-to-clear interrupt registers on non-prefetchable BARs?
> return NULL;
>
> /*
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260910143440.3865663-2-ardb+git@google.com?part=1
next prev parent reply other threads:[~2026-09-10 14:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 14:34 [RFC PATCH] PCI: Tolerate non-prefetchable 64-bit BARs in prefetchable windows Ard Biesheuvel
2026-09-10 14:42 ` sashiko-bot [this message]
2026-09-10 17:31 ` Ilpo Järvinen
2026-09-10 21:04 ` Ard Biesheuvel
2026-09-11 9:27 ` Ilpo Järvinen
2026-09-11 10:01 ` Ard Biesheuvel
2026-09-11 10:14 ` Lorenzo Pieralisi
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