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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:25 -0700 (PDT) From: Qiang Yu Subject: [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Date: Tue, 15 Sep 2026 23:04:20 -0700 Message-Id: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAGQxqmoC/yXMUQrCMBBF0a2U+TaQFBKpWxEJafqsIzLWTCtC6 d4b9fNw4a6kKAylU7NSwZuVn1LhDg3lW5IRhodqam0bbOe8SQ8eJU6ZEVl4jorXAsmItQbjj85 1NvVIPlB9TAVX/vz+58vfuvR35Pk7pW3bAQe4xpuBAAAA X-Change-ID: 20260915-align_pcie_init_sequence_0916-571190abea56 To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=2301; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=Q85aXDMwvbpzbdqQZSLnN+pKhKHeKEyGsGA98e+i4Hg=; b=VanMV8I3b6x/UKi8Pi0uPylqTjCwhgLHtLLspbcP88b+CZT1gM9u0udCt6lZrEVLqwiiDCt3u OIkB+RytzmiAGVjxv/dp8txVevQMPr4OSRhvgqLg1w87iUb4GxONhWv X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: DtpeYibeSMSy66PaYMrpAT4j4AQ19DX8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfXwpFk4dMvQloZ it5t2GMijMYswp2uY7LNV8ZZw1x3cec6vJKlVbepJKq8F0PpQJDMi5RSUYFRSDCDXbK8fwK623l QU3M+DQdmE6gOttl8GX8d2/hJhs1Znu3eOegrN/bCYfPxf2kUnbqp+I0i+ylfEfFPeWMCE/WGAg d4Wbr3vZBy1d7n+X2e9ucfdls4bgK/bQTqPOijyonX41xX8l+VFt3pLQh0q1EYD4fTtANaMzrEU QC9bUU+lMTVd54h7WGIbtWbgpRE9w3b//KC4Pek1ktypSi7oRKsQOX9s6TmjKs77xxI8ltZPPMV vy2P7Ltv+N5sne1NnD1qyNA7RX3uqTHz1HYM14phGx9R9k2CjKxgfZILMgbCb2KsDWNoGA34ykv FW6x5sv53KQKNIGXwU45hk2t/f5y8xpykK73EUPpdIFnVXBfR94xs6oIS3a3XwiYlKHK9oWdUIe WSxZFD1GeIHkeykS6BA== X-Authority-Analysis: v=2.4 cv=eKmGH3p1 c=1 sm=1 tr=0 ts=6aaa316b cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=Riq-LXKwlQ56QxmQOhoA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfX57NqIuJY5GiL 68wMFE9DqH+mNa5YqE3C9QQQCp+pR+nzT2LSw2MgrGO1V1PoWmKVeMWJ7l2baxWTa2/rEwacjRT SUgR8UZ/y/XCOkjakBanR3JaRqoj5hI= X-Proofpoint-GUID: DtpeYibeSMSy66PaYMrpAT4j4AQ19DX8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 HPG requires the controller/PHY GDSCs to be powered up and all clocks enabled, then the controller's reset and the PHY's reset toggled together as one group, with PARF_DEVICE_TYPE set right after. This series adds the callbacks needed on both sides to realize that sequence: a phy_reset() call the controller makes as part of its own reset, and matching phy_ops::init/phy_ops::reset on the PHY side. Patches 1-2 move phy_init()/phy_exit() into the RC and EP controllers' own init/deinit paths, add a phy_reset() call grouped with each controller's own reset, and move the PARF_DEVICE_TYPE write to right after that reset group. Patches 3-4 update the two PHY drivers these controllers can use (phy-qcom-qmp-pcie[-multiphy].c) to implement phy_ops::init/reset, matching phy_ops::power_on to what's left once phy_ops::init/phy_ops::reset are pulled out. phy_init()/phy_reset() are no-ops against a phy_ops without phy_ops::init/phy_ops::reset, so patches 1-2 don't change behavior on any platform by themselves; patches 3-4 are what actually change the sequence for the platforms using those two PHY drivers. Other PHY drivers this series doesn't touch (phy-qcom-qmp-pcie-msm8996.c, phy-qcom-uniphy-pcie-28lp.c, phy-qcom-pcie2.c) are either unaffected (no phy_ops::init/phy_ops::reset) or only see their phy_init()/phy_exit() call site moved without a sequence change. Signed-off-by: Qiang Yu --- Qiang Yu (4): PCI: qcom: Move PHY init and add PHY reset call to align with HPG PCI: qcom-ep: Move PHY init and drive PHY reset to align with HPG phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on drivers/pci/controller/dwc/pcie-qcom-ep.c | 26 +-- drivers/pci/controller/dwc/pcie-qcom.c | 165 ++++++++++++++----- drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c | 94 ++++------- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 184 ++++++++++------------ 4 files changed, 257 insertions(+), 212 deletions(-) --- base-commit: e6e35979777d646fe3c7c94dca7dd32fb25d45f4 change-id: 20260915-align_pcie_init_sequence_0916-571190abea56 Best regards, -- Qiang Yu