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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bfb19f8cesm4740083eec.2.2026.09.15.23.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 23:04:27 -0700 (PDT) From: Qiang Yu Date: Tue, 15 Sep 2026 23:04:22 -0700 Subject: [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset to align with HPG Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260915-align_pcie_init_sequence_0916-v1-2-0b2195836f30@oss.qualcomm.com> References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789538665; l=3449; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=h3fngNlkhZEZKpBHI/IT3xTrpcNvbLpoMF3Il2nEqag=; b=eTZfXLMDSIpr2rD0kW+QmRWdp9HNs5rYFTSCCvbAdhqFxpkC15bmD+pT/64Xq3BBABZm7nE6r kif1GcsJYCKBDLi+hJrEpTvhL5VVFDqdA8qCq0ZLA5sRh1Fa7EGYA62 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfXzf6iTeZF9Pe1 vq7iJt6p/NGjs+XavGlP14F3U9KeefGfcFVk4gLjAvUSia2kcbjTnCjTbD3Ty+D8o879hlP5ZQy ebHmW1AzZwx5jInb7xmGNgyalPtv+Ts= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDA3NiBTYWx0ZWRfXyGOxlAZpDVhM sRTqM4lR4fi+tXc+/mm363yU4pCwpHNCXgajiqvraTvkss72hnXOrS5ulRpp4speC9NJ8BSvQ+S 4AcGKpQyybMKobWMF2NXHcxAa4G7PWFJ5C0y+re7HZRQ5k9GuskqhDjUb1BgxTngBDcZO/YwCCQ GdlxIoXCIQyX8wlEoL0P4Kyu8w3IjR/vmRIfztYmtYj79qddH+b8ULaELi4sDAIJc/R2r6yMckv O626oqteMN4WGg7uHTpJDdBnh0vvPlxgJQnfBnBum5r319O4mPN9nc5W3/9cxec+ElSb708paqd mpze1HLiB3BifuNjO0XTJq224rn+MVxDag+BWwTgH05nRJ9+oOoywUMZ47f/rmndJtGGG2crn57 N2cOXlsSQoebWKEwbYykEDR78f/td+76u5IyvQuKd8ANvlZW+LPw5SmqiilD6yth/0SmHGG8sbe fsTjr0nWK2FYYUGp8Wg== X-Proofpoint-GUID: BYPbkxAaBQQT1mVOTpBLj6LyMSScNgD7 X-Proofpoint-ORIG-GUID: BYPbkxAaBQQT1mVOTpBLj6LyMSScNgD7 X-Authority-Analysis: v=2.4 cv=PcZqFShd c=1 sm=1 tr=0 ts=6aaa316d cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=PV8ZVrNDrE42_2bsUUYA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160076 HPG requires the GDSC to be powered up and all PHY/controller clocks enabled before the controller's core reset and the PHY's reset are toggled together as one atomic group, with PARF_DEVICE_TYPE set right after that reset group, same as the RC-mode change. Move phy_init() ahead of the controller's own clock enable, and fold phy_reset() into the core reset assert/deassert. phy_power_on() keeps running afterwards. Also move the PARF_DEVICE_TYPE write out of qcom_pcie_perst_deassert() to right after the reset group, in qcom_pcie_enable_resources(). phy_reset() and phy_init are currently a no-op against the PHY this driver uses, so the init sequence doesn't change yet; it actually changes once the PHY driver later implements .reset. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 8364696a1b98..cd7725d277c5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -228,7 +228,7 @@ struct qcom_pcie_ep { int perst_irq; }; -static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) +static int qcom_pcie_ep_phy_core_reset(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; struct device *dev = pci->dev; @@ -242,6 +242,12 @@ static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep) usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX); + ret = phy_reset(pcie_ep->phy); + if (ret) { + dev_err(dev, "Cannot reset phy\n"); + return ret; + } + ret = reset_control_deassert(pcie_ep->core_reset); if (ret) { dev_err(dev, "Cannot de-assert core reset\n"); @@ -332,25 +338,25 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) struct dw_pcie *pci = &pcie_ep->pci; int ret; - ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); + ret = phy_init(pcie_ep->phy); if (ret) return ret; - ret = qcom_pcie_ep_core_reset(pcie_ep); + ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); if (ret) - goto err_disable_clk; + goto err_phy_exit; - ret = phy_init(pcie_ep->phy); + ret = qcom_pcie_ep_phy_core_reset(pcie_ep); if (ret) goto err_disable_clk; ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); if (ret) - goto err_phy_exit; + goto err_disable_clk; ret = phy_power_on(pcie_ep->phy); if (ret) - goto err_phy_exit; + goto err_disable_clk; /* * Some Qualcomm platforms require interconnect bandwidth constraints @@ -370,10 +376,10 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) err_phy_off: phy_power_off(pcie_ep->phy); -err_phy_exit: - phy_exit(pcie_ep->phy); err_disable_clk: clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); +err_phy_exit: + phy_exit(pcie_ep->phy); return ret; } @@ -390,8 +396,8 @@ static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); - phy_exit(pcie_ep->phy); clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); + phy_exit(pcie_ep->phy); } static int qcom_pcie_perst_deassert(struct dw_pcie *pci) -- 2.34.1