Re: [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] dts: pci: static ranges will not be updated dynamically due to existing DT node
- [Low] dts: pci-ep-bus node has unit address but no reg property
--

commit 1c7c7d7922bcd554a385a9dab10bfbe2a5cf71bb
Author: Alex Elder <elder@riscstar.com>

arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses

This commit adds endpoint buses for a PCIe switch connected via the second
PCI segment (0001) on the RB3gen2 platform. It defines devicetree nodes
representing these buses, including the mapping of each BAR's address
range to its local address space.

> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 3bb5fca8e2b13..59fbb0444d9b7 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
[ ... ]
> @@ -955,11 +955,41 @@ pcie@3,0 {
>  			bus-range = <0x5 0xff>;
>  
>  			dev@0,0 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50000 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				/* Ranges will be updated dynamically */
> +				ranges = <0x0 0x0 0x0  0x83050000 0x0 0x0 0x0 0x4000>,
> +					 <0x2 0x0 0x0  0x83050000 0x0 0x0 0x0 0x80000>,
> +					 <0x4 0x0 0x0  0x83050000 0x0 0x0 0x0 0x200000>;

[Severity: High]
Will these placeholder ranges actually be updated dynamically at runtime? 
Because the dev@0,0 node is statically defined in the devicetree, it appears
the PCI core's of_pci_make_dev_node() will find it during quirk processing
(via pci_device_to_OF_node()) and return early. 

If that happens, of_pci_add_properties() won't be called, leaving these
overlapping dummy physical addresses in place and potentially breaking MMIO
translation for child devices.

> +
> +				pci-ep-bus@4 {

[Severity: Low]
Does this node name trigger a dtc compiler warning? Defining a unit address
(@4) without a corresponding reg property violates the Devicetree
specification and will cause a unit_address_vs_reg warning.

> +					compatible = "simple-bus";
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					/* Map 0x0-0x1fffff to BAR 4 */
> +					ranges = <0x0  0x4 0x0 0x0  0x200000>;
> +				};
>  			};
>  
>  			dev@0,1 {
> +				compatible = "pci1179,0220";
>  				reg = <0x50100 0x0 0x0 0x0 0x0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				/* Ranges will be updated dynamically */
> +				ranges = <0x0 0x0 0x0  0x83050100 0x0 0x0 0x0 0x4000>,
> +					 <0x2 0x0 0x0  0x83050100 0x0 0x0 0x0 0x80000>,
> +					 <0x4 0x0 0x0  0x83050100 0x0 0x0 0x0 0x200000>;

[Severity: High]
Similarly for dev@0,1, will this static definition prevent dynamic ranges
updates? If of_pci_add_properties() is skipped due to the node already
existing, the dummy physical addresses will remain and could cause register
corruption or crashes if child drivers probe here.

> +
> +				pci-ep-bus@4 {

[Severity: Low]
This node is also named with @4 but does not define a reg property, which
can trigger a dtc unit_address_vs_reg warning.

> +					compatible = "simple-bus";
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					/* Map 0x0-0x1fffff to BAR 4 */
> +					ranges = <0x0  0x4 0x0 0x0  0x200000>;
> +				};
>  			};
>  		};
>  	};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915031038.1087264-1-elder@riscstar.com?part=3