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Tue, 15 Sep 2026 16:22:08 -0700 (PDT) X-Received: by 2002:a05:6a21:9090:b0:3d0:e034:a26f with SMTP id adf61e73a8af0-3dd5f5d8672mr1167615637.17.1789514527903; Tue, 15 Sep 2026 16:22:07 -0700 (PDT) Received: from localhost ([50.35.44.179]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bf5b0520asm2203060eec.27.2026.09.15.16.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 16:22:07 -0700 (PDT) Date: Tue, 15 Sep 2026 16:22:04 -0700 From: Jonathan Cameron To: Nicolin Chen Cc: , , , , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: Re: [PATCH v5 10/15] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Message-ID: <20260915162204.000054b9@oss.qualcomm.com> In-Reply-To: References: Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE1MDM0MSBTYWx0ZWRfX0zOub/BD1F5M CHgHqjPYBq7rIh7kTQFnlJEAOAxr6tjJl1sHY/3Z+V9iKZWfSja3qwXhUg+ARgCPi5H2C1IP8r5 taRaloVBvUq/ftZVD7uqwg/Le4paBPQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE1MDM0MSBTYWx0ZWRfX7N7b0Qt8hjEG vXKQm21LtyboaPO10KUVJidR3cbcvnZYjlGceV/cgzWQlPspfZDzHmOhU5GXF8PEWoWfWZ2FBCT mhn5dCGaFiRbeDD1VyuLsaOr+XPZvNluroDI5uoZYRY9MW/cl/z+3snY+UR8RjUzc3j+vU4Pd/l k588orPjlE7VXAa+rC/MI/xFEdA6BvHOfn10LojI5UTuwkMYqsZLNuYowZdBklsnZX1avk7q07S +/BjpDwphZGOyEkZ/mkkDIKA9PSzWrnX2kH6Nt0aSsQRvC65ro24Tb6LTjLPcohvumGuOziw20t ZZm9ENtxsSmDuIILo582VehjXdosoKnATGfcjtCa4GxQMRc4KMHSoLIGYYMy4MbgoVxLJS1s9Q0 nS5wNRApNzya+FB9RQBkbx0iT2VqBP2NpmI5ZRDNEd5HhMOlRkeVXS2qHeYa1oDdwsVONcGZ47y TvwEzHGdzn6y2ToqQTA== X-Proofpoint-GUID: PDpAh_kfE5S_KpKtJXBqLssH0RTlsfB4 X-Proofpoint-ORIG-GUID: PDpAh_kfE5S_KpKtJXBqLssH0RTlsfB4 X-Authority-Analysis: v=2.4 cv=PcZqFShd c=1 sm=1 tr=0 ts=6aa9d321 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=aNnz9XPx1a4JIXSYt2cE/A==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=Ikd4Dj_1AAAA:8 a=EUspDBNiAAAA:8 a=h35TsNJSbmzmzvWWgmEA:9 a=CjuIK1q_8ugA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-15_05,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609150341 On Tue, 15 Sep 2026 09:38:22 -0700 Nicolin Chen wrote: > For a PRI-enabled master, convert every PRIQ entry into an iopf_fault and > report it through iommu_report_device_fault(). > > For an unknown StreamID or a master without PRI enabled, keep the existing > LAST-page DENY path. Merge its two messages into one ratelimited line so a > faulty device cannot flood the kernel log. > > Discard any PASID Stop Marker (LRW = 0b100) prior to the fault report and > the DENY fallback both, because a Stop Marker does not expect a response. > The IOPF infrastructure requires the driver to discard it, as per the doc > at iommu_report_device_fault(). This also matches the intel-iommu code. > > When SSV is clear, the same LRW encoding is a PRI Page Request that expects > a response, so let it fall through. > > Note that master->pri_enabled will only be set by a later change, once all > the PRI paths are ready. > > Co-developed-by: Barak Biber > Signed-off-by: Barak Biber > Co-developed-by: Stefan Kaestle > Signed-off-by: Stefan Kaestle > Signed-off-by: Malak Marrid > Signed-off-by: Nicolin Chen Reviewed-by: Jonathan Cameron