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From: sashiko-bot@kernel.org
To: "Mario Limonciello" <mario.limonciello@amd.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 2/2] PCI: Put PCIe bridges with downstream devices into D3 at hibernate
Date: Wed, 16 Sep 2026 05:23:19 +0000	[thread overview]
Message-ID: <20260916052319.EC3E81F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260916051034.180226-3-mario.limonciello@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] pci: config space corruption on hibernation abort due to missing D3 guard
--

commit 99f9dafa720163cc3dfac6ce20da883f888fb896
Author: Mario Limonciello (AMD) <superm1@kernel.org>

PCI: Put PCIe bridges with downstream devices into D3 at hibernate

During S3 suspend, pci_pm_suspend_noirq() puts PCIe bridges with
downstream devices into a low-power state. This commit aligns the
hibernate poweroff_noirq flow to use pci_pm_suspend_noirq_common(),
ensuring bridges with active children are also put into D3.

> diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
> --- a/drivers/pci/pci-driver.c
> +++ b/drivers/pci/pci-driver.c
[ ... ]
> @@ -1280,8 +1283,9 @@ static int pci_pm_poweroff_noirq(struct device *dev)
>  			return error;
>  	}
>  
> -	if (!pci_dev->state_saved && !pci_has_subordinate(pci_dev))
> -		pci_prepare_to_sleep(pci_dev);
> +	skip_bus_pm = pci_pm_suspend_noirq_common(pci_dev);

[Severity: High]
Could this lead to configuration space corruption if a hibernation aborts?

If a driver's poweroff_noirq callback puts the device into a low-power
state (like D3) but fails to save its state, calling
pci_pm_suspend_noirq_common() here will unconditionally invoke
pci_save_state().

Because the device is already in D3, reading the configuration registers
in pci_save_state() will populate saved_config_space with 0xFFFFFFFF
garbage.

If the hibernation process subsequently aborts, the PM core executes
pci_pm_restore_noirq(), which will blindly write this 0xFFFFFFFF garbage
back to the device's configuration registers (BARs, command registers, etc).
This will likely cause a system crash upon subsequent memory-mapped I/O
access.

Does pci_pm_poweroff_noirq() need the same explicit D3 safety guard that
the S3 suspend_noirq path uses to prevent reading config space from a
powered-down device?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916051034.180226-1-mario.limonciello@amd.com?part=2

  reply	other threads:[~2026-09-16  5:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16  5:10 [PATCH v4 0/2] Unfiy PCI suspend and hibernate paths Mario Limonciello
2026-09-16  5:10 ` [PATCH v4 1/2] PCI/PM: Split out code from pci_pm_suspend_noirq() into helper Mario Limonciello
2026-09-16  5:15   ` sashiko-bot
2026-09-16 13:49   ` Rafael J. Wysocki (Intel)
2026-09-16  5:10 ` [PATCH v4 2/2] PCI: Put PCIe bridges with downstream devices into D3 at hibernate Mario Limonciello
2026-09-16  5:23   ` sashiko-bot [this message]
2026-09-16  5:36     ` Mario Limonciello
2026-09-16 13:56   ` Rafael J. Wysocki (Intel)

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