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Fri, 18 Sep 2026 14:20:46 -0700 (PDT) Received: from yurypm-new-58lzp.sjc.aristanetworks.com ([74.123.28.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144d55e71a4sm1004948c88.13.2026.09.18.14.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2026 14:20:45 -0700 (PDT) From: Yury Murashka To: bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yury Murashka Subject: [PATCH] PCI: pciehp: Add PLX quirk for missing Command Completed events Date: Fri, 18 Sep 2026 21:19:26 +0000 Message-ID: <20260918211926.1480-1-yurypm@arista.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit All PLX PEX 8600- and 8700-series data books say the Command Completed bit is set only after the Hot Plug Controller completes a command that changes the Attention Indicator Control, Power Indicator Control, Power Controller Control, or Electromechanical Interlock Control fields. It is not set after writes that only change the Presence Detect Changed Enable or Command Completed Interrupt Enable bits. Consequently, pciehp waits for Command Completed after changing these notification Enable bits and logs a timeout. This behavior exactly matches the conditions described when quirk_cmd_compl() was first added: both controllers report completion only when the same four Control fields change and fail to report completion for notification Enable-only writes. Add only the PLX PEX 8600- and 8700-series switches on which this fix was tested to quirk_cmd_compl(). This makes pciehp mark Enable-only writes complete immediately while continuing to wait for commands that change Control fields. Signed-off-by: Yury Murashka --- drivers/pci/hotplug/pciehp_hpc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 4c62140a3..5450aa6c7 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -1122,3 +1122,17 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401, PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8717, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8725, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8749, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8604, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8608, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8609, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_PLX, 0x8614, + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); base-commit: 5dd1818b15d98d4a20806cd00b1b40320b06004f -- 2.51.0