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Wed, 23 Sep 2026 00:18:58 -0700 From: Manikanta Maddireddy To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , "Krzysztof Wilczynski" , Bjorn Helgaas , CC: Rob Herring , Thierry Reding , Jonathan Hunter , Vidya Sagar , Niklas Cassel , , , Manikanta Maddireddy Subject: [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Date: Wed, 23 Sep 2026 12:47:02 +0530 Message-ID: <20260923071706.1134320-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260923071706.1134320-1-mmaddireddy@nvidia.com> References: <20260923071706.1134320-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002314:EE_|DS0PR12MB7948:EE_ X-MS-Office365-Filtering-Correlation-Id: 0789e342-4cc1-4e53-795e-08df1942fd07 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|23010399003|82310400026|1800799024|36860700016|10067099003|11063799006|56012099006|22082099003|18002099003; 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Keep the existing shift-based definitions for now so current users keep building until their call sites are converted. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-designware.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0735ae940924..c4db241547be 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -278,14 +278,17 @@ #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 #define EVENT_COUNTER_ENABLE_SHIFT 2 +#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) #define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) #define EVENT_COUNTER_EVENT_SEL_SHIFT 16 +#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16) #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 #define EVENT_COUNTER_EVENT_L1_1 0x7 #define EVENT_COUNTER_EVENT_L1_2 0x8 #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 +#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_GROUP_5 0x5 #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc -- 2.34.1