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Thu, 24 Sep 2026 05:42:46 -0700 (PDT) Received: from maclinux ([2803:c600:9110:8ba5:43a9:9b8b:ebdc:6411]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f986e465sm13466113c88.9.2026.09.24.05.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 05:42:45 -0700 (PDT) From: =?UTF-8?q?Francisco=20Beltr=C3=A1n=20Millal=C3=A9n?= To: bhelgaas@google.com, linux-pci@vger.kernel.org Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/4] PCI/PM: Do not save or restore the config space of an inaccessible device Date: Thu, 24 Sep 2026 09:42:17 -0300 Message-ID: <20260924124221.12374-1-fbeltranmillalen@gmail.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When a PCI device becomes inaccessible while the system is suspending, pci_save_state() happily stores 0xFFFFFFFF into all 16 dwords of the saved config space, and pci_restore_state() writes that back on resume -- to a device that by then *is* responding again. On a MacBookPro14,3 (Intel Alpine Ridge Thunderbolt 3) this is not theoretical. The upstream bridge of the Thunderbolt switch stops responding during suspend, and on resume the restore leaves it with: - the Secondary Bus Reset bit asserted (0xFF contains PCI_BRIDGE_CTL_BUS_RESET), - primary/secondary/subordinate bus numbers set to ff/ff/ff, - the link retrained down from 8 GT/s to 2.5 GT/s. The visible effect is a 65-second resume while the kernel waits for devices that can no longer be reached, followed by the removal of both xHCI controllers: every USB-C port on the machine is gone until reboot. The series makes the save path refuse to snapshot a device that is not there, the restore path refuse to write back a snapshot that is all ones, and teaches one more caller not to mistake an absent device for a working link. Patch 1 makes the USB PCI HCD honour the pci_save_state() return value, which it currently ignores. It is a fix in its own right -- pci_save_state() can already fail today -- and it is placed first so that no patch in the series introduces an error condition before its caller knows how to handle it. Measured on the affected machine, comparing the same suspend/resume cycle with and without the series: - resume time for the affected bridge: 65 s -> 1 s; - the bridge keeps its bus numbers (04/05/79) and its 8 GT/s link, with no Secondary Bus Reset asserted; - the xHCI behind it survives the cycle: 1 of 2 controllers instead of 0 of 2, and 4 USB buses instead of 2. v2 of this work fixes two defects found in review of v1: a pci_WARN_ONCE() that the first version could trigger in pci_pm_suspend_noirq(), and a partially written snapshot -- v1 could leave dev->saved_config_space half updated if the device disappeared while it was being read. v2 reads into a temporary buffer and only commits it after re-checking that the device is still there. Both were verified on hardware: the warning count went from 1 and 1 to 0 and 0, and the per-device resume timings are unchanged to within 0.01%. Tested on 6.18.49 on the machine described above. I do not have other affected hardware, so wider testing of the PCI core changes would be welcome.