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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a00d0f66cfsm12682225e9.14.2026.09.28.11.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 11:56:27 -0700 (PDT) Date: Mon, 28 Sep 2026 19:56:26 +0100 From: David Laight To: Ilpo =?UTF-8?B?SsOkcnZpbmVu?= Cc: Bjorn Helgaas , "Rafael J. Wysocki" , Maciej Grochowski , Nikolas Joshua Britton , Geramy Loveless , Eric Auger , Alexey Fomenko , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , linux-pci@vger.kernel.org, LKML Subject: Re: [PATCH 5/5] PCI/quirks: Avoid certain BAR 0 address with igb Message-ID: <20260928195626.1e878a20@pumpkin> In-Reply-To: <77f7d79b-d3fb-0576-0b6d-eef4efd8d634@linux.intel.com> References: <20260924202056.GA2001522@bhelgaas> <447e3daa-c8a5-2b0c-2c6d-3f3eb92e94cc@linux.intel.com> <20260928141936.2539ad5f@pumpkin> <77f7d79b-d3fb-0576-0b6d-eef4efd8d634@linux.intel.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Mon, 28 Sep 2026 17:30:41 +0300 (EEST) Ilpo J=C3=A4rvinen wrote: > On Mon, 28 Sep 2026, David Laight wrote: >=20 > > On Mon, 28 Sep 2026 15:20:13 +0300 (EEST) > > Ilpo J=C3=A4rvinen wrote: > > =20 > > > On Thu, 24 Sep 2026, Bjorn Helgaas wrote: > > > =20 > > > > [+cc Rafael, ACPI resource question] > > > >=20 > > > > On Wed, Sep 23, 2026 at 04:17:55PM +0300, Ilpo J=C3=A4rvinen wrote:= =20 > > > > > While testing the resource placement changes, my tests hit a case= where > > > > > igb fails to probe when BAR 0 is placed at 0x9c000000: > > > > >=20 > > > > > 90000000-9cffffff : PCI Bus 0000:a0 > > > > > - 90000000-902fffff : PCI Bus 0000:a1 > > > > > - 90000000-900fffff : 0000:a1:00.0 > > > > > - 90000000-900fffff : igb > > > > > - 90100000-901fffff : 0000:a1:00.0 > > > > > - 90200000-90203fff : 0000:a1:00.0 > > > > > - 90200000-90203fff : igb > > > > > + 9be00000-9c0fffff : PCI Bus 0000:a1 =20 > >=20 > > Is that valid? > > I'm no expect but I wouldn't expect an address range to cross a power o= f 2 boundary. =20 >=20 > Hi, >=20 > Bridge windows are defined by a base/limit pair, both with 1M granularity= .=20 > There's nothing that disallows a bridge window crossing a power of 2=20 > boundary in the spec (AFAIK). >=20 > Note that after this quirk is applied reshuffling the device BAR=20 > resources, the same crossing is still there and the device works. >=20 > Perhaps you mixed this up with BAR resources that indeed must to be=20 > naturally aligned. >=20 I did say I wasn't an expert :-) The PCIe book I've got is just over 20 years old (only 1000 pages). I know rather more about the TLPs - we had a problem with some fpga logic that didn't like getting two completions for a single read. But it would be consistent with something 'not liking' BAR0 being at 9bxxxxxx and BAR1 at 9cxxxxxx. David