Re: [PATCH v3 2/2] PCI: Allow 64-bit non-prefetchable BARs in prefetchable windows

[sashiko-bot@kernel.org]

> From: Ard Biesheuvel <ardb@kernel.org>
> 
> The non-prefetchable memory window of a PCI-to-PCI bridge can only
> decode 32-bit addresses, and so non-prefetchable BARs of devices below a
> bridge can only be allocated from the part of the host bridge memory
> space below 4 GB. This is the case even for 64-bit BARs, which could
> easily be placed above 4 GB if there was a bridge window to put them in,
> and on many platforms, 32-bit addressable MMIO space is scarce.
> 
> The PCIe spec addresses this in the implementation note "Additional
> Guidance on the Prefetchable Bit in Memory Space BARs" (PCIe r7.0, sec
> 7.5.1.2.1): on PCIe, setting the Prefetchable bit of a BAR still permits
> correct operation even if the range has read side effects or cannot
> tolerate write merging, as long as the entire path from the host to the
> device is PCIe, given that PCIe Memory Reads always carry an explicit
> [ ... ]
>     IORESOURCE_PREFETCH on the BAR), and this change does not modify the
>     flags of any BAR.)
> 
> Assisted-by: LLM
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

Sashiko has reviewed this patch and found no issues. It looks great!

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