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From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration
Date: Thu, 01 Oct 2026 10:12:18 +0000	[thread overview]
Message-ID: <20261001101218.841621F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20261001092227.3004747-11-smadhavan@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] cxl: Misplaced error logging suppresses PCI_COMMAND restore failure logs
--

commit 62840404e5420d7cde318d8a3f21873bf84154cf
Author: Srirangan Madhavan <smadhavan@nvidia.com>

cxl: Cache endpoint HDM state during PCI enumeration

This commit introduces a cache for CXL HDM state during PCI enumeration
to support driver-independent resets. It temporarily modifies PCI_COMMAND
to access MMIO, reads the cache state, and then restores the PCI_COMMAND
register.

> diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
> index 8d2fbc49a06fb..c3f53c1b93fd8 100644
> --- a/drivers/cxl/core/resource.c
> +++ b/drivers/cxl/core/resource.c

[ ... ]

> +static struct cxl_hdm_info *cxl_pci_hdm_read_info(struct pci_dev *pdev,
> +						  struct cxl_register_map *map,
> +						  int dvsec)
> +{

[ ... ]

> +	info = __cxl_pci_hdm_read_info(pdev, map, dvsec);
> +	rc = pci_write_config_word(pdev, PCI_COMMAND, command);
> +	if (!rc)
> +		return info;
> +
> +	if (IS_ERR(info)) {
> +		pci_err(pdev,
> +			"failed to restore PCI_COMMAND after CXL HDM cache init: %d\n",
> +			pcibios_err_to_errno(rc));
> +		return info;
> +	}
> +
> +	kfree(info);
> +	return ERR_PTR(pcibios_err_to_errno(rc));
> +}

[Severity: Medium]
Is the error logging for the PCI_COMMAND restore correctly scoped here?

If __cxl_pci_hdm_read_info() succeeds (info is a valid pointer) but the
subsequent pci_write_config_word() to restore PCI_COMMAND fails, this skips
the if (IS_ERR(info)) block entirely.

As a result, it correctly frees info and returns an error pointer, but
silently suppresses the pci_err() log about the restore failure. Conversely,
if both the read and the restore fail, it logs the restore failure but
returns the read failure. 

Does this code unintentionally hide the restore failure logs when the cache
read is successful?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261001092227.3004747-1-smadhavan@nvidia.com?part=10

  reply	other threads:[~2026-10-01 10:12 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-01  9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01  9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-01  9:25   ` sashiko-bot
2026-10-02  9:33   ` Richard Cheng
2026-10-07 12:07   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:48   ` Richard Cheng
2026-10-07 12:22   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-01  9:30   ` sashiko-bot
2026-10-02  9:49   ` Richard Cheng
2026-10-07 12:29   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-01  9:49   ` sashiko-bot
2026-10-02 10:17   ` Richard Cheng
2026-10-02 19:07   ` Dave Jiang
2026-10-07 12:34   ` Li Ming
2026-10-01  9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-02 19:59   ` Dave Jiang
2026-10-07 13:12     ` Li Ming
2026-10-07 16:23       ` Dave Jiang
2026-10-08 13:18         ` Li Ming
2026-10-08 15:19           ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01  9:31   ` sashiko-bot
2026-10-05 21:42   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-01 10:02   ` sashiko-bot
2026-10-02 21:46   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-01  9:35   ` sashiko-bot
2026-10-02 21:50   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-01  9:37   ` sashiko-bot
2026-10-02 23:57   ` Dave Jiang
2026-10-01  9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 10:12   ` sashiko-bot [this message]
2026-10-06 15:39   ` Dave Jiang
2026-10-07 19:37     ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 10:18   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-01 10:23   ` sashiko-bot
2026-10-02  8:06   ` Richard Cheng
2026-10-07 19:44   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 10:31   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 10:49   ` sashiko-bot
2026-10-07 19:49   ` Alison Schofield
2026-10-01  9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01 11:02   ` sashiko-bot
2026-10-01  9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-01 11:12   ` sashiko-bot

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