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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f2f045ca4sm171937385a.29.2026.10.17.10.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2026 10:49:13 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xI8Wu-00000004sUa-33rg; Sat, 17 Oct 2026 14:49:12 -0300 Date: Sat, 17 Oct 2026 14:49:12 -0300 From: Jason Gunthorpe To: Nicolin Chen Cc: Pranjal Shrivastava , iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Radu Rendec , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Greg Kroah-Hartman , rafael@kernel.org, Danilo Krummrich , driver-core@lists.linux.dev Subject: Re: [PATCH v11 11/16] iommu/arm-smmu-v3: Add CMDQ_PROD_STOP_FLAG to gate CMDQ submissions Message-ID: <20261017174912.GK14213@ziepe.ca> References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-12-praan@google.com> <20261002164748.GD3481470@ziepe.ca> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Oct 06, 2026 at 10:26:41AM -0700, Nicolin Chen wrote: > > pci_dev_reset_iommu_prepare/done() pair (with slight refactoring) in EP's > > suspend/resume? > > That sounds right to me, though a different API for suspend/resume > will be required. And call them in pci_pm_runtime_suspend/resume() > maybe. > > Jason, how do you think about this? Maybe lets just start by refusing power management when ATS is on? For PCIe devices too? It isn't just ARM that has this issue, every iommu is busted if you suspend the PCI device while an ATS domain is still active.. Jason