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Mon, 19 Oct 2026 13:25:17 -0700 (PDT) Received: from maclinux ([2803:c600:9110:8ba5:1c75:eeaa:b22f:20dc]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ea9b128725sm11194050e0c.0.2026.10.19.13.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 13:25:17 -0700 (PDT) From: =?UTF-8?q?Francisco=20Beltr=C3=A1n=20Millal=C3=A9n?= To: Bjorn Helgaas , linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Alan Stern , Greg Kroah-Hartman , Lukas Wunner , Farhan Ali , Andreas Noever , Mika Westerberg , Yehezkel Bernat , Darrell Gum , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] PCI: Do not mistake an absent device for an active link Date: Mon, 19 Oct 2026 17:24:45 -0300 Message-ID: <20261019202445.38259-3-fbeltranmillalen@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261019202445.38259-1-fbeltranmillalen@gmail.com> References: <20261019202445.38259-1-fbeltranmillalen@gmail.com> X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When an inaccessible bridge's Link Status register reads as 0xffff, both PCI_EXP_LNKSTA_DLLLA and PCI_EXP_LNKSTA_LT appear set. The link wait code then takes the inaccessible bridge for an active link: - pci_bridge_wait_for_secondary_bus(), for ports up to 5 GT/s, decides that the link is up and waits PCIE_RESET_READY_POLL_MS for the device below it; - pcie_wait_for_link_status(), used for faster ports and by pcie_retrain_link(), reports success at once when waiting for an active link, and times out after PCIE_LINK_RETRAIN_TIMEOUT_MS when waiting for LT to clear. Treat an all-ones read as the device being gone. All callers of pcie_wait_for_link_status() and pcie_retrain_link() treat any non-zero return as failure. On a MacBookPro14,3 whose Thunderbolt controller does not come back from S3, the downstream ports of the controller are 2.5 GT/s ports that no longer answer. Resume spent about 65 seconds waiting for the xHCI controller behind one of them ("not ready 65535ms after resume"); with the pci_bridge_wait_for_secondary_bus() change it gives up on that controller after about one second. That machine never reaches pcie_wait_for_link_status() in this situation, so that part has not been tested. Assisted-by: LLM Signed-off-by: Francisco Beltrán Millalén Tested-by: Darrell Gum --- v3: - No change, apart from adding Darrell's Tested-by from v2 (was 3/3). v2: - Also cover pcie_wait_for_link_status(). drivers/pci/pci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index eacaa1e71a83..24b51dd0f9cc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4604,8 +4604,8 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) * @use_lt: Use the LT bit if TRUE, or the DLLLA bit if FALSE. * @active: Waiting for active or inactive? * - * Return 0 if successful, or -ETIMEDOUT if status has not changed within - * PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds. + * Return 0 if successful, -ENODEV if @pdev is not accessible, or -ETIMEDOUT + * if status has not changed within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds. */ static int pcie_wait_for_link_status(struct pci_dev *pdev, bool use_lt, bool active) @@ -4620,6 +4620,9 @@ static int pcie_wait_for_link_status(struct pci_dev *pdev, end_jiffies = jiffies + msecs_to_jiffies(PCIE_LINK_RETRAIN_TIMEOUT_MS); do { pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta); + /* All ones means @pdev is gone; it would look like an active link */ + if (PCI_POSSIBLE_ERROR(lnksta)) + return -ENODEV; if ((lnksta & lnksta_mask) == lnksta_match) return 0; msleep(1); @@ -4642,8 +4645,9 @@ static int pcie_wait_for_link_status(struct pci_dev *pdev, * according to @use_lt. It is not verified whether the use of the DLLLA * bit is valid. * - * Return 0 if successful, or -ETIMEDOUT if training has not completed - * within PCIE_LINK_RETRAIN_TIMEOUT_MS milliseconds. + * Return 0 if successful, -ENODEV if @pdev is not accessible, or -ETIMEDOUT + * if training has not completed within PCIE_LINK_RETRAIN_TIMEOUT_MS + * milliseconds. */ int pcie_retrain_link(struct pci_dev *pdev, bool use_lt) { @@ -4876,8 +4880,10 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) if (!dev->link_active_reporting) return -ENOTTY; + /* All ones means @dev is gone; it would look like an active link */ pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &status); - if (!(status & PCI_EXP_LNKSTA_DLLLA)) + if (PCI_POSSIBLE_ERROR(status) || + !(status & PCI_EXP_LNKSTA_DLLLA)) return -ENOTTY; return pci_dev_wait(child, reset_type,