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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LY0PR12MB727857.namprd12.prod.outlook.com (2603:10b6:408:3ba::5) by LV2PR12MB6014.namprd12.prod.outlook.com (2603:10b6:408:170::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.569.8; Thu, 29 Oct 2026 14:57:27 +0000 Received: from LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522]) by LY0PR12MB727857.namprd12.prod.outlook.com ([fe80::843e:82cd:41ca:f522%5]) with mapi id 15.21.0569.008; Thu, 29 Oct 2026 14:57:27 +0000 From: Srirangan Madhavan To: Alison Schofield , Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Li Ming , Alex Williamson , vsethi@nvidia.com, alwilliamson@nvidia.com, Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , linux-tegra@vger.kernel.org, Srirangan Madhavan Subject: [PATCH v16 05/18] cxl: Introduce endpoint HDM decoder settings Date: Thu, 29 Oct 2026 14:56:50 +0000 Message-ID: <20261029145703.2185231-6-smadhavan@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261029145703.2185231-1-smadhavan@nvidia.com> References: <20261029145703.2185231-1-smadhavan@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MW4PR04CA0271.namprd04.prod.outlook.com (2603:10b6:303:89::6) To LY0PR12MB727857.namprd12.prod.outlook.com (2603:10b6:408:3ba::5) X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LY0PR12MB727857:EE_|LV2PR12MB6014:EE_ X-MS-Office365-Filtering-Correlation-Id: fb277d96-a784-4f40-efcd-08df35ccf299 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|23010399003|376014|366016|1800799024|921020|261028144727099003|11063799006|56012099006|261009223027099003|261021123027099003|261022113327099003|261021121427099003|261026121527099003|261022105027099003|261026140227099003|261022075727099003|10067099003|22082099003|18002099003|6133799003; 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Share range programming, but keep endpoint skip and switch target-list writes in their respective commit paths. Separate commit initiation from completion waiting so reset restoration can reuse register programming without changing normal DPA-lock policy. Signed-off-by: Srirangan Madhavan Reviewed-by: Dave Jiang Reviewed-by: Li Ming Assisted-by: LLM --- drivers/cxl/core/core.h | 8 ++++ drivers/cxl/core/hdm.c | 95 ++++++++++++++++++++++++++++------------- include/cxl/hdm.h | 19 +++++++++ 3 files changed, 92 insertions(+), 30 deletions(-) create mode 100644 include/cxl/hdm.h diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 983d7690c3a5..fb14b222f3ca 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -7,6 +7,8 @@ #include #include +struct cxl_endpoint_decoder_settings; + extern const struct device_type cxl_nvdimm_bridge_type; extern const struct device_type cxl_nvdimm_type; extern const struct device_type cxl_pmu_type; @@ -139,6 +141,12 @@ struct cxl_rwsem { extern struct cxl_rwsem cxl_rwsem; +void cxl_commit_start_endpoint(const struct cxl_endpoint_decoder_settings *settings, + void __iomem *hdm); +void cxl_commit_start_switch(const struct cxl_decoder_config *config, + u64 targets, void __iomem *hdm); +int cxld_await_commit(void __iomem *hdm, int id); + int cxl_memdev_init(void); void cxl_memdev_exit(void); void cxl_mbox_init(void); diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 9e05032a5426..af445f1b9798 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -3,6 +3,7 @@ #include #include #include +#include #include "cxlmem.h" #include "core.h" @@ -707,7 +708,7 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size) return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled); } -static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) +static void cxld_set_interleave(const struct cxl_decoder_config *config, u32 *ctrl) { u16 eig; u8 eiw; @@ -716,12 +717,12 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) * Input validation ensures these warns never fire, but otherwise * suppress unititalized variable usage warnings. */ - if (WARN_ONCE(ways_to_eiw(cxld->config.interleave_ways, &eiw), - "invalid interleave_ways: %d\n", cxld->config.interleave_ways)) + if (WARN_ONCE(ways_to_eiw(config->interleave_ways, &eiw), + "invalid interleave_ways: %d\n", config->interleave_ways)) return; - if (WARN_ONCE(granularity_to_eig(cxld->config.interleave_granularity, &eig), + if (WARN_ONCE(granularity_to_eig(config->interleave_granularity, &eig), "invalid interleave_granularity: %d\n", - cxld->config.interleave_granularity)) + config->interleave_granularity)) return; u32p_replace_bits(ctrl, eig, CXL_HDM_DECODER0_CTRL_IG_MASK); @@ -729,10 +730,10 @@ static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) *ctrl |= CXL_HDM_DECODER0_CTRL_COMMIT; } -static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) +static void cxld_set_type(const struct cxl_decoder_config *config, u32 *ctrl) { u32p_replace_bits(ctrl, - !!(cxld->config.target_type == CXL_DECODER_HOSTONLYMEM), + !!(config->target_type == CXL_DECODER_HOSTONLYMEM), CXL_HDM_DECODER0_CTRL_HOSTONLY); } @@ -764,7 +765,7 @@ static void cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt) * clock skew and other marginal behavior */ #define COMMIT_TIMEOUT_MS 20 -static int cxld_await_commit(void __iomem *hdm, int id) +int cxld_await_commit(void __iomem *hdm, int id) { u32 ctrl; int i; @@ -784,45 +785,79 @@ static int cxld_await_commit(void __iomem *hdm, int id) return -ETIMEDOUT; } -static void setup_hw_decoder(struct cxl_decoder *cxld, void __iomem *hdm) +static u32 cxl_hdm_write_range(void __iomem *hdm, + const struct cxl_decoder_config *config) { - int id = cxld->config.id; - u64 base, size; + u64 size = range_len(&config->hpa_range); + u64 base = config->hpa_range.start; + int id = config->id; u32 ctrl; - /* common decoder settings */ - ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(cxld->config.id)); - cxld_set_interleave(cxld, &ctrl); - cxld_set_type(cxld, &ctrl); - base = cxld->config.hpa_range.start; - size = range_len(&cxld->config.hpa_range); + ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id)); + cxld_set_interleave(config, &ctrl); + cxld_set_type(config, &ctrl); writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id)); writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id)); writel(upper_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id)); writel(lower_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id)); + return ctrl; +} + +void cxl_commit_start_endpoint(const struct cxl_endpoint_decoder_settings *settings, + void __iomem *hdm) +{ + int id = settings->config.id; + u32 ctrl; + + lockdep_assert_held(&cxl_rwsem.dpa); + ctrl = cxl_hdm_write_range(hdm, &settings->config); + writel(upper_32_bits(settings->skip), hdm + CXL_HDM_DECODER0_SKIP_HIGH(id)); + writel(lower_32_bits(settings->skip), hdm + CXL_HDM_DECODER0_SKIP_LOW(id)); + writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id)); +} + +void cxl_commit_start_switch(const struct cxl_decoder_config *config, + u64 targets, void __iomem *hdm) +{ + int id = config->id; + u32 ctrl; + + lockdep_assert_held(&cxl_rwsem.dpa); + ctrl = cxl_hdm_write_range(hdm, config); + writel(upper_32_bits(targets), hdm + CXL_HDM_DECODER0_TL_HIGH(id)); + writel(lower_32_bits(targets), hdm + CXL_HDM_DECODER0_TL_LOW(id)); + writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id)); +} + +static void +cxl_endpoint_decoder_snapshot(struct cxl_endpoint_decoder *cxled, + struct cxl_endpoint_decoder_settings *settings) +{ + lockdep_assert_held(&cxl_rwsem.dpa); + + *settings = (struct cxl_endpoint_decoder_settings) { + .config = cxled->cxld.config, + .skip = cxled->skip, + }; +} + +static void setup_hw_decoder(struct cxl_decoder *cxld, void __iomem *hdm) +{ + struct cxl_endpoint_decoder_settings settings; if (is_switch_decoder(&cxld->dev)) { struct cxl_switch_decoder *cxlsd = to_cxl_switch_decoder(&cxld->dev); - void __iomem *tl_hi = hdm + CXL_HDM_DECODER0_TL_HIGH(id); - void __iomem *tl_lo = hdm + CXL_HDM_DECODER0_TL_LOW(id); u64 targets; cxlsd_set_targets(cxlsd, &targets); - writel(upper_32_bits(targets), tl_hi); - writel(lower_32_bits(targets), tl_lo); + cxl_commit_start_switch(&cxld->config, targets, hdm); } else { - struct cxl_endpoint_decoder *cxled = - to_cxl_endpoint_decoder(&cxld->dev); - void __iomem *sk_hi = hdm + CXL_HDM_DECODER0_SKIP_HIGH(id); - void __iomem *sk_lo = hdm + CXL_HDM_DECODER0_SKIP_LOW(id); - - writel(upper_32_bits(cxled->skip), sk_hi); - writel(lower_32_bits(cxled->skip), sk_lo); + cxl_endpoint_decoder_snapshot(to_cxl_endpoint_decoder(&cxld->dev), + &settings); + cxl_commit_start_endpoint(&settings, hdm); } - - writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id)); } static int cxl_decoder_commit(struct cxl_decoder *cxld) diff --git a/include/cxl/hdm.h b/include/cxl/hdm.h new file mode 100644 index 000000000000..219b9bb67440 --- /dev/null +++ b/include/cxl/hdm.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2026 NVIDIA Corporation & Affiliates */ +#ifndef __CXL_HDM_H__ +#define __CXL_HDM_H__ + +#include +#include + +/** + * struct cxl_endpoint_decoder_settings - endpoint HDM decoder programming + * @config: common decoder configuration + * @skip: length of DPA space skipped before this decoder's DPA mapping + */ +struct cxl_endpoint_decoder_settings { + struct cxl_decoder_config config; + u64 skip; +}; + +#endif /* __CXL_HDM_H__ */ -- 2.43.0