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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c2de58sm1260017c88.12.2026.11.03.13.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 13:02:22 -0800 (PST) Date: Tue, 3 Nov 2026 13:02:14 -0800 From: Jonathan Cameron To: Nicolin Chen Cc: Jason Gunthorpe , , Bjorn Helgaas , Will Deacon , Robin Murphy , , Len Brown , Joerg Roedel , Kevin Tian , Jonathan Cameron , Dave Jiang , Dan Williams , , , , Subject: Re: [PATCH v1 2/5] PCI/CXL: Probe the underlying bus reset in cxl_reset_bus_function() Message-ID: <20261103130214.00000b82@oss.qualcomm.com> In-Reply-To: References: <6c09d2f78d4bb9db7f49fa14a6550f5176721121.1793729707.git.nicolinc@nvidia.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAzMDA4MyBTYWx0ZWRfX9Qn8UsCwOxun 92TpDvchNVN9bIkonN2KRmo31rFHCltoUjZy+GEkNh7CQ0wn+dk3HkzuraLTltSboKjOKJNP2yH M+VU9ZQwSKR0IhZBIr2/UDgbmyYaplDxELK1aeKSY50HjkdnWqPONGiGdnCxyOUu0sgkUm9PC40 ATnBPaLP0oAOc5uIb28UahCnQ6O2YEeeHnlmONXdN8HJzW9yE2mK/1bKYSmuLg5Tfdh2X4DhExt oStVRaQAgjwylZ/BG8mqH1y0rl37Zd2OGqm7cJBlOKgVYuGNTKoWS9v3kHc7m+OzvKJDRR/KwLO yQ3qoUKZyW7+UCj1cnohoGD7OqXSc13qZYrYl1YxOXQrr4YafFZEsF4zjxnyYTb6fMRTPu2kANb JuVFE41E4GgrMW1x5F3i8dDPFosDx5uc1HhVntF3VB8PYHDTWF4MimaPMjLwaeAby1gzeurHToj Tt3xHDpKGwleS4DIR7g== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAzMDA4MyBTYWx0ZWRfX2Y482/icM5pa FANhqUopaLzLv5mj6CehzsftzrJvN4e4tTh5SFxBfi5W90nX60crt8MfSn/Hu/BMkmuF00iChHn LGsjMj4/1OCChCsW6ojurXuCG4unZqU= X-Proofpoint-GUID: qGImwD3kdQuCzabY-Ssb3d4yLqHsV7BE X-Proofpoint-ORIG-GUID: qGImwD3kdQuCzabY-Ssb3d4yLqHsV7BE X-Authority-Analysis: v=2.4 cv=As17T+9P c=1 sm=1 tr=0 ts=6aea4be0 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=Ikd4Dj_1AAAA:8 a=EUspDBNiAAAA:8 a=Zdewuh5ThNVhPH2xqRoA:9 a=CjuIK1q_8ugA:10 a=O8hF6Hzn-FEA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-03_04,2026-11-03_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611030083 On Tue, 3 Nov 2026 10:44:29 -0800 Nicolin Chen wrote: > On Tue, Nov 03, 2026 at 10:33:43AM -0800, Nicolin Chen wrote: > > cxl_reset_bus_function() reports "supported" to a probe after checking only > > that the upstream bridge carries a CXL port DVSEC. The underlying bus reset > > can still be unavailable, e.g. on a bus shared with other devices, so both > > the reset_methods[] array and the reset_method sysfs node end up listing a > > "cxl_bus" that is guaranteed to fail with -ENOTTY when it is attempted. > > > > Probe the underlying pci_dev_reset_slot_function() and then, if it is not > > applicable, pci_parent_bus_reset(). These are the same two checks that the > > actual reset runs, so a shared-bus CXL device no longer advertises a method > > that can never succeed. > > > > Probing via pci_reset_bus_function() would not work: its cxl_sbr_masked() > > check rejects every CXL port with a masked SBR, while the do-reset path in > > this function unmasks the SBR before resetting. Such a port would wrongly > > probe as unsupported. > > > > Move the port control register read above the probe branch as well, so that > > probe runs the same checks. That read asserts no reset, and a failure means > > the device cannot be reset this way, which is a probe-time answer. > > > > Also pass an explicit PCI_RESET_DO_RESET at the do-reset call site, since > > probe is always false at that point. > > > > Fixes: 53c49b6e6dd2e ("PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports") > > Signed-off-by: Nicolin Chen > > Ah, I missed Jonathan's review tag during the split: > https://lore.kernel.org/linux-iommu/20260926001311.7c4be583@jic23-hlaptop/ > > Jonathan, would you mind giving another review tag here? It's the > exact same patch that you reviewed. Sorry for the inconvenience. > Reviewed-by: Jonathan Cameron > Nicolin