Re: [PATCH v4 07/10] PCI/IDE: Add IDE establishment helpers

[Arto Merilainen <amerilainen@nvidia.com>]

On 8.8.2025 20.26, dan.j.williams@intel.com wrote:
> Arto Merilainen wrote:
>> The first revision of this patch had address association register
>> programming but it has since been removed. Could you comment if there is
>> a reason for this change?
> 
> We chatted about it around this point in the original review thread [1].
> tl;dr SEV-TIO and TDX Connect did not see a strict need for it. However,
> the expectation was always to circle back and revive it if it turned out
> later to be required.

Thank you for the reference. I suppose it is ok to rely on the default 
streams on the first iteration, and add a follow-up patch in the ARM CCA 
device assignment support series in case it is the only architecture 
that depends on them.

> 
>> Some background: This might be problematic for ARM CCA. I recall seeing
>> a comment stating that the address association register programming can
>> be skipped on some architectures (e.g., apparently AMD uses a separate
>> table that contains the StreamID) but on ARM CCA the StreamID
>> association AFAIK happens through these registers.
> 
> Can you confirm and perhaps work with Aneesh to propose an incremental
> patch to add that support back? It might be something that we let the
> low level TSM driver control. Like an additional address association
> object that can be attached to 'struct pci_ide' by the low level TSM
> driver.

Aneesh, could you perhaps extend the IDE driver by adding the RP address 
association register programming in the next revision of the DA support 
series?

I think the EP side programming won't be relevant until we get to the 
P2P use-cases.

> 
> The messy part is sparse device MMIO layout vs limited association
> blocks and this is where SEV-TIO and TDX Connect have other mechanisms
> to do that stream-id association.

Despite the potential sparsity, I think there needs to be only three 
address association register blocks per SEL_IDE block: The routing is 
based on the type-1 configuration space header which defines only three 
ranges (32bit BAR, 64bit BAR, IO). When enabling IDE between an RP and 
an EP, the SEL_IDE address association registers in the RP can be 
programmed with the same ranges used in the type-1 header in the switch 
upstream from the EP.

That said, if the RP implements less than three address association 
registers per SEL_SID, this scheme won't work.

(I vaguely recall that the PCIe spec might forbid IORd/IOWr TLPs when 
selective IDE streams are used so the limit might in fact be two instead 
three...)

- R2