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Thu, 13 Nov 2025 23:46:56 -0600 Received: from [10.24.73.74] (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5AE5kq4n1456754; Thu, 13 Nov 2025 23:46:53 -0600 Message-ID: <250d2b94d5785e70530200e00c1f0f46fde4311b.camel@ti.com> Subject: Re: [PATCH] PCI: cadence: Kconfig: change PCIE_CADENCE configs from tristate to bool From: Siddharth Vadapalli To: Arnd Bergmann , Lorenzo Pieralisi , Krzysztof =?UTF-8?Q?Wilczy=C5=84ski?= , "Manivannan Sadhasivam" , Rob Herring , , Chen Wang , "Kishon Vijay Abraham I" CC: , , , , , Date: Fri, 14 Nov 2025 11:17:08 +0530 In-Reply-To: <084b804f-2999-4f8d-8372-43cfbf0c0d28@app.fastmail.com> References: <20251113092721.3757387-1-s-vadapalli@ti.com> <084b804f-2999-4f8d-8372-43cfbf0c0d28@app.fastmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1-1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000207:EE_|DS0PR10MB6824:EE_ X-MS-Office365-Filtering-Correlation-Id: 40c8233b-56fd-43ca-97e8-08de23413ca1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|32650700017|1800799024|82310400026|36860700013; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2025 05:47:02.9518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40c8233b-56fd-43ca-97e8-08de23413ca1 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000207.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR10MB6824 On Thu, 2025-11-13 at 11:13 +0100, Arnd Bergmann wrote: Hello Arnd, > On Thu, Nov 13, 2025, at 10:27, Siddharth Vadapalli wrote: > > The drivers associated with the PCIE_CADENCE, PCIE_CADENCE_HOST AND > > PCIE_CADENCE_EP configs are used by multiple vendor drivers and serve a= s a > > library of helpers. Since the vendor drivers could individually be buil= t > > as built-in or as loadable modules, it is possible to select a build > > configuration wherein a vendor driver is built-in while the library is > > built as a loadable module. This will result in a build error as report= ed > > in the 'Closes' link below. > >=20 > > Address the build error by changing the library configs to be 'bool' > > instead of 'tristate'. > >=20 > > Reported-by: kernel test robot > > Closes:=20 > > https://lore.kernel.org/oe-kbuild-all/202511111705.MZ7ls8Hm-lkp@intel.c= om/ > > Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") > > Cc: > > Signed-off-by: Siddharth Vadapalli >=20 > I really think there has to be a better solution here, this is not > an unusual problem. >=20 > > @@ -4,16 +4,16 @@ menu "Cadence-based PCIe controllers" > > depends on PCI > >=20 > > config PCIE_CADENCE > > - tristate > > + bool > >=20 > > config PCIE_CADENCE_HOST > > - tristate > > + bool > > depends on OF > > select IRQ_DOMAIN > > select PCIE_CADENCE > >=20 > > config PCIE_CADENCE_EP > > - tristate > > + bool > > depends on OF > > depends on PCI_ENDPOINT > > select PCIE_CADENCE >=20 > I think the easiest way would be to leave PCIE_CADENCE as > a 'tristate' symbol but make the other two 'bool', and then > adjust the Makefile logic to use CONFIG_PCIE_CADENCE as > the thing that controls how the individual drivers are built. >=20 > That way, if any platform specific driver is built-in, both > the EP and HOST support are built-in or disabled but never > loadable modules. As long as all platform drivers are > loadable modules, so would be the base support. Thank you for the suggestion. I think that the following Makefile changes will be sufficient and Kconfig doesn't need to be modified: diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 5e23f8539ecc..1a97c9b249b8 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,4 +4,6 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o +pci_j721e-y :=3D pci-j721e.o pcie-cadence.o obj-$(CONFIG_PCIE_SG2042_HOST) +=3D pcie-sg2042.o +pci_sg2042_host-y :=3D pci-sg2042.o pcie-cadence.o If either of PCI_J721E or SG2042_HOST is selected as a built-in module, then pcie-cadence-host.c, pcie-cadence-ep.c and pcie-cadence.c drivers will be built-in. If both PCI_J721E and SG2042_HOST are selected as loadable modules, only then the library drivers will be enabled as loadable modules. Please let me know what you think. Regards, Siddharth.