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[219.120.4.122]) by smtp.gmail.com with ESMTPSA id y37sm29705052pgk.78.2019.04.04.09.20.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Apr 2019 09:20:32 -0700 (PDT) Subject: Re: [PATCH V5 6/6] PCI: rcar: Fix 64bit MSI message address handling To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, Marek Vasut , Geert Uytterhoeven , Phil Edworthy , Simon Horman , Wolfram Sang , linux-renesas-soc@vger.kernel.org References: <20190402013307.20912-1-marek.vasut@gmail.com> <20190402013307.20912-6-marek.vasut@gmail.com> <20190404092833.GA13236@red-moon> From: Marek Vasut Openpgp: preference=signencrypt Message-ID: <267aa1b1-9761-aff7-8462-8efc644083bd@gmail.com> Date: Thu, 4 Apr 2019 17:48:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <20190404092833.GA13236@red-moon> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 4/4/19 11:28 AM, Lorenzo Pieralisi wrote: > On Tue, Apr 02, 2019 at 03:33:07AM +0200, marek.vasut@gmail.com wrote: >> From: Marek Vasut >> >> The MSI message address in the RC address space can be 64 bit. The >> R-Car PCIe RC supports such a 64bit MSI message address as well. >> The code currently uses virt_to_phys(__get_free_pages()) to obtain >> a reserved page for the MSI message address, and the return value >> of which can be a 64 bit physical address on 64 bit system. >> >> However, the driver only programs PCIEMSIALR register with the bottom >> 32 bits of the virt_to_phys(__get_free_pages()) return value and does >> not program the top 32 bits into PCIEMSIAUR, but rather programs the >> PCIEMSIAUR register with 0x0. This worked fine on older 32 bit R-Car >> SoCs, however may fail on new 64 bit R-Car SoCs. >> >> Since from a PCIe controller perspective, an inbound MSI is a memory >> write to a special address (in case of this controller, defined by >> the value in PCIEMSIAUR:PCIEMSIALR), which triggers an interrupt, but >> never hits the DRAM _and_ because allocation of an MSI by a PCIe card >> driver obtains the MSI message address by reading PCIEMSIAUR:PCIEMSIALR >> in rcar_msi_setup_irqs(), incorrectly programmed PCIEMSIAUR cannot >> cause memory corruption or other issues. >> >> There is however the possibility that if virt_to_phys(__get_free_pages()) >> returned address above the 32bit boundary _and_ PCIEMSIAUR was programmed >> to 0x0 _and_ if the system had physical RAM at the address matching the >> value of PCIEMSIALR, a PCIe card driver could allocate a buffer with a >> physical address matching the value of PCIEMSIALR and a remote write to >> such a buffer by a PCIe card would trigger a spurious MSI. >> >> Signed-off-by: Marek Vasut >> Cc: Geert Uytterhoeven >> Cc: Phil Edworthy >> Cc: Simon Horman >> Cc: Wolfram Sang >> Cc: linux-renesas-soc@vger.kernel.org >> To: linux-pci@vger.kernel.org >> Reviewed-by: Geert Uytterhoeven >> --- >> V2: - s/it's/its/ in commit message >> - Add R-B from Geert >> V3: - Reworded commit message and thus dropped Geerts R-B >> V4: - Add Geert's R-B again >> V5: - Rebase on next/master 20190401 >> - Use {lower,upper}_32_bits() instead of >> 32 > > If that's the only reason you resent this series I will add the > lower_32_bits() code myself. Yes, you asked me to resend the whole series after the bot complained. > Please do not rebase on top of next, apply code on top of a fixed -rc1 > (we are currently using v5.1-rc1) and if there are dependencies on code > already queued do let us know, we will handle conflicts in next > ourselves. So do you want me to resend this one more time ? -- Best regards, Marek Vasut