From: Bert Karwatzki <spasswolf@web.de>
To: "Christian König" <christian.koenig@amd.com>,
"Mario Limonciello" <superm1@kernel.org>,
linux-kernel@vger.kernel.org
Cc: linux-next@vger.kernel.org, regressions@lists.linux.dev,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
spasswolf@web.de
Subject: Re: [REGRESSION 00/04] Crash during resume of pcie bridge
Date: Fri, 31 Oct 2025 14:47:20 +0100 [thread overview]
Message-ID: <26bf82303f661cdd34e4e8c16997e33eb21d1ee4.camel@web.de> (raw)
In-Reply-To: <f18bafacbd8316c9623658e2935f8fc3b276af64.camel@web.de>
Upon closer inspection I noticed that the PCIe bandwitdth has been reduced:
>
> [76621.870884] [ T140] pcieport 0000:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
> [76621.870977] [ T140] pcieport 0000:02:00.0: Unable to change power state from D3cold to D0, device inaccessible
> [76621.876006] [ T140] pci_bus 0000:03: busn_res: [bus 03] is released
> [76621.878237] [ T140] pci_bus 0000:02: busn_res: [bus 02-03] is released
> [76621.879867] [ T140] pcieport 0000:00:01.1: pciehp: Slot(0): Card present
> [76621.879873] [ T140] pcieport 0000:00:01.1: pciehp: Slot(0): Link Up
> [76622.006565] [ T140] pci 0000:01:00.0: [1002:1478] type 01 class 0x060400 PCIe Switch Upstream Port
> [76622.006606] [ T140] pci 0000:01:00.0: BAR 0 [mem 0xfcc00000-0xfcc03fff]
> [76622.006616] [ T140] pci 0000:01:00.0: PCI bridge to [bus 02-03]
> [76622.006630] [ T140] pci 0000:01:00.0: bridge window [mem 0xfca00000-0xfcbfffff]
> [76622.006644] [ T140] pci 0000:01:00.0: bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
> [76622.006772] [ T140] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
The PCIe band with seems to be have been reduce to PCIe 1.0 (2.5GT/s):
> [76622.006874] [ T140] pci 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x8 link at 0000:00:01.1 (capable of 126.024 Gb/s with
> 16.0 GT/s PCIe x8 link)
>
> Bert Karwatzki
This is the same message from system startup (here it's PCIe 3.0 (8.0GT/s), which is the PCIe version
of the CPU (AMD Ryzen 7 5800H with Radeon Graphics)):
[ 0.289221] [ T1] pci 0000:01:00.0: 63.008 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x8 link at 0000:00:01.1 (capable of 126.024 Gb/s with
16.0 GT/s PCIe x8 link)
Bert Karwatzki
next prev parent reply other threads:[~2025-10-31 13:47 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 12:09 [REGRESSION 00/04] Crash during resume of pcie bridge Bert Karwatzki
2025-10-06 12:09 ` [REGRESSION 01/04] " Bert Karwatzki
2025-10-06 12:09 ` [REGRESSION 02/04] " Bert Karwatzki
2025-10-06 12:09 ` [REGRESSION 03/04] " Bert Karwatzki
2025-10-06 12:09 ` [REGRESSION 04/04] " Bert Karwatzki
2025-10-06 12:39 ` [REGRESSION 00/04] " Christian König
2025-10-06 16:22 ` Bert Karwatzki
2025-10-07 6:50 ` Bert Karwatzki
2025-10-07 21:33 ` Mario Limonciello
2025-10-13 16:29 ` Bert Karwatzki
2025-10-13 18:51 ` Mario Limonciello
2025-10-14 10:50 ` Christian König
[not found] ` <1853e2af7f70cf726df278137b6d2d89d9d9dc82.camel@web.de>
2025-10-31 13:38 ` Bert Karwatzki
2025-10-31 13:47 ` Bert Karwatzki [this message]
2025-10-31 18:35 ` Bert Karwatzki
2025-11-05 11:44 ` Bert Karwatzki
2025-11-05 21:31 ` Mario Limonciello (AMD) (kernel.org)
2025-11-07 13:09 ` Bert Karwatzki
2025-11-07 17:09 ` Bert Karwatzki
2025-11-10 13:33 ` Christian König
2025-11-16 21:08 ` Crash during resume of pcie bridge due to infinite loop in ACPICA Bert Karwatzki
2025-11-17 16:40 ` Rafael J. Wysocki
2025-11-24 22:34 ` Bert Karwatzki
2025-11-25 19:46 ` Rafael J. Wysocki
2025-11-27 0:08 ` Bert Karwatzki
2025-11-27 13:02 ` Rafael J. Wysocki
2025-11-28 20:47 ` Bert Karwatzki
2025-12-02 18:59 ` Rafael J. Wysocki
2025-12-02 19:53 ` Bert Karwatzki
2025-12-02 20:01 ` Rafael J. Wysocki
2025-12-05 10:05 ` Crash during resume of pcie bridge due to incorrect error handling Bert Karwatzki
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