* [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
@ 2014-02-20 5:22 Mohit Kumar
2014-02-20 6:56 ` Rajeev kumar
0 siblings, 1 reply; 4+ messages in thread
From: Mohit Kumar @ 2014-02-20 5:22 UTC (permalink / raw)
To: jg1.han; +Cc: Mohit Kumar, Bjorn Helgaas, spear-devel, linux-pci
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of lines as 4 */
+ /* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
--
1.7.0.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
2014-02-20 5:22 Mohit Kumar
@ 2014-02-20 6:56 ` Rajeev kumar
2014-02-20 8:29 ` Mohit KUMAR DCG
0 siblings, 1 reply; 4+ messages in thread
From: Rajeev kumar @ 2014-02-20 6:56 UTC (permalink / raw)
To: Mohit KUMAR
Cc: jg1.han@samsung.com, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
subject line
PCI: designware: Fix comment for setting number of lanes
~Rajeev
On 2/20/2014 10:52 AM, Mohit KUMAR wrote:
> Corrects comment for setting number of lanes.
>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Jingoo Han<jg1.han@samsung.com>
> Cc: Bjorn Helgaas<bhelgass@google.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 6d23d8c..391966f 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> u32 membase;
> u32 memlimit;
>
> - /* set the number of lines as 4 */
> + /* set the number of lanes */
> dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL,&val);
> val&= ~PORT_LINK_MODE_MASK;
> switch (pp->lanes) {
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
2014-02-20 6:56 ` Rajeev kumar
@ 2014-02-20 8:29 ` Mohit KUMAR DCG
0 siblings, 0 replies; 4+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 8:29 UTC (permalink / raw)
To: Rajeev KUMAR
Cc: jg1.han@samsung.com, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
SGVsbG8gUmFqZWV2LA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFJh
amVldiBLVU1BUg0KPiBTZW50OiBUaHVyc2RheSwgRmVicnVhcnkgMjAsIDIwMTQgMTI6MjYgUE0N
Cj4gVG86IE1vaGl0IEtVTUFSIERDRw0KPiBDYzogamcxLmhhbkBzYW1zdW5nLmNvbTsgQmpvcm4g
SGVsZ2Fhczsgc3BlYXItZGV2ZWw7IGxpbnV4LQ0KPiBwY2lAdmdlci5rZXJuZWwub3JnDQo+IFN1
YmplY3Q6IFJlOiBbUEFUQ0ggMS8yXSBQQ0k6ZGVzaWdud2FyZTpGaXggY29tbWVudCBmb3Igc2V0
dGluZyBudW1iZXIgb2YNCj4gbGFuZXMNCj4gDQo+IHN1YmplY3QgbGluZQ0KPiANCj4gUENJOiBk
ZXNpZ253YXJlOiBGaXggY29tbWVudCBmb3Igc2V0dGluZyBudW1iZXIgb2YgbGFuZXMNCj4gDQot
IHRoYW5rcywgd2lsbCBwdXQgc3BhY2VzLg0KDQpSZWdhcmRzDQpNb2hpdA0K
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
@ 2014-02-21 0:59 Jingoo Han
0 siblings, 0 replies; 4+ messages in thread
From: Jingoo Han @ 2014-02-21 0:59 UTC (permalink / raw)
To: Mohit Kumar
Cc: Bjorn Helgaas, spear-devel@list.st.com, linux-pci@vger.kernel.org,
Jingoo Han
T24gRmViIDIwLCAyMDE0IDE0OjIyIChHTVQrMDk6MDApLCBNb2hpdCBLdW1hciB3cm90ZToNCj4g
DQo+IENvcnJlY3RzIGNvbW1lbnQgZm9yIHNldHRpbmcgbnVtYmVyIG9mIGxhbmVzLg0KPiANCj4g
U2lnbmVkLW9mZi1ieTogTW9oaXQgS3VtYXIgPG1vaGl0Lmt1bWFyQHN0LmNvbT4NCj4gQ2M6IEpp
bmdvbyBIYW4gPGpnMS5oYW5Ac2Ftc3VuZy5jb20+DQo+IENjOiBCam9ybiBIZWxnYWFzIDxiaGVs
Z2Fzc0Bnb29nbGUuY29tPg0KPiBDYzogc3BlYXItZGV2ZWxAbGlzdC5zdC5jb20NCj4gQ2M6IGxp
bnV4LXBjaUB2Z2VyLmtlcm5lbC5vcmcNCg0KQWNrZWQtYnk6IEppbmdvbyBIYW4gPGpnMS5oYW5A
c2Ftc3VuZy5jb20+DQoNClJpZ2h0LCB0aGFua3MuDQoNCkJlc3QgcmVnYXJkcywNCkppbmdvbyBI
YW4NCg0KPiAtLS0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMgfCAgICAy
ICstDQo+ICAxIGZpbGVzIGNoYW5nZWQsIDEgaW5zZXJ0aW9ucygrKSwgMSBkZWxldGlvbnMoLSkN
Cj4gDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jIGIv
ZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuYw0KPiBpbmRleCA2ZDIzZDhjLi4zOTE5
NjZmIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+
ICsrKyBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMNCj4gQEAgLTc2Niw3ICs3
NjYsNyBAQCB2b2lkIGR3X3BjaWVfc2V0dXBfcmMoc3RydWN0IHBjaWVfcG9ydCAqcHApDQo+ICAJ
dTMyIG1lbWJhc2U7DQo+ICAJdTMyIG1lbWxpbWl0Ow0KPiAgDQo+IC0JLyogc2V0IHRoZSBudW1i
ZXIgb2YgbGluZXMgYXMgNCAqLw0KPiArCS8qIHNldCB0aGUgbnVtYmVyIG9mIGxhbmVzICovDQo+
ICAJZHdfcGNpZV9yZWFkbF9yYyhwcCwgUENJRV9QT1JUX0xJTktfQ09OVFJPTCwgJnZhbCk7DQo+
ICAJdmFsICY9IH5QT1JUX0xJTktfTU9ERV9NQVNLOw0KPiAgCXN3aXRjaCAocHAtPmxhbmVzKSB7
DQo+IC0tIA0KPiAxLjcuMC4x
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-02-21 0:59 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-02-21 0:59 [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Jingoo Han
-- strict thread matches above, loose matches on Subject: below --
2014-02-20 5:22 Mohit Kumar
2014-02-20 6:56 ` Rajeev kumar
2014-02-20 8:29 ` Mohit KUMAR DCG
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).