From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Ajay Agarwal <ajayagarwal@google.com>, Jian-Hong Pan <jhp@endlessos.org>
Cc: "David E. Box" <david.e.box@linux.intel.com>,
Johan Hovold <johan+linaro@kernel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Manu Gautam <manugautam@google.com>,
Sajid Dalvi <sdalvi@google.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Vidya Sagar <vidyas@nvidia.com>,
Shuai Xue <xueshuai@linux.alibaba.com>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI/ASPM: Save downstream port L1ss control when saving for upstream
Date: Wed, 27 Nov 2024 12:54:33 +0200 (EET) [thread overview]
Message-ID: <2aceef41-6d65-2eab-8339-07f874be6f41@linux.intel.com> (raw)
In-Reply-To: <20241127033758.3974931-1-ajayagarwal@google.com>
Adding Jian-Hong.
There's already another patch under discussion to the same problem:
https://patchwork.kernel.org/project/linux-pci/patch/20241115072200.37509-3-jhp@endlessos.org/
--
i.
On Wed, 27 Nov 2024, Ajay Agarwal wrote:
> It is possible that the downstream port's L1ss registers were not
> saved after the initial configuration performed in the function
> aspm_calc_l12_info() during the child bus probe. If the upstream
> port config space is saved-restored due to some reason, the
> downstream port L1ss registers will be overwritten with stale
> configuration due to the logic present in
> pci_restore_aspm_l1ss_state(). So, attempt to save the downstream
> port L1ss registers when we are at the upstream component.
>
> Signed-off-by: Ajay Agarwal <ajayagarwal@google.com>
> ---
> drivers/pci/pcie/aspm.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index cee2365e54b8..769a305fad63 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -99,6 +99,19 @@ void pci_save_aspm_l1ss_state(struct pci_dev *pdev)
> cap = &save_state->cap.data[0];
> pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++);
> pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++);
> +
> + /*
> + * It is possible that the downstream port's L1ss registers were not
> + * saved after the initial configuration performed in the function
> + * aspm_calc_l12_info() during the child bus probe. If the upstream port
> + * config space is saved-restored due to some reason, the downstream
> + * port L1ss registers will be overwritten with stale configuration due
> + * to the logic present in pci_restore_aspm_l1ss_state(). So, attempt to
> + * save the downstream port L1ss registers when we are at the upstream
> + * component.
> + */
> + if (!pcie_downstream_port(pdev))
> + pci_save_aspm_l1ss_state(pdev->bus->self);
> }
>
> void pci_restore_aspm_l1ss_state(struct pci_dev *pdev)
>
prev parent reply other threads:[~2024-11-27 10:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-27 3:37 [PATCH] PCI/ASPM: Save downstream port L1ss control when saving for upstream Ajay Agarwal
2024-11-27 10:54 ` Ilpo Järvinen [this message]
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