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Thu, 17 Apr 2025 02:12:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQyKNgE0DokKtvPIYouYE1uOOI7So2YqEjxzqZuyFFiQfJrMgw7yOOs6D0q9vCJ2ghjk5ZDA== X-Received: by 2002:a17:903:2f85:b0:223:6744:bfb9 with SMTP id d9443c01a7336-22c35973405mr86070015ad.41.1744881120660; Thu, 17 Apr 2025 02:12:00 -0700 (PDT) Received: from [10.92.199.136] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c33fe9810sm28564065ad.249.2025.04.17.02.11.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Apr 2025 02:12:00 -0700 (PDT) Message-ID: <2c0b0929-0610-3e99-03be-a50e9f5f323b@oss.qualcomm.com> Date: Thu, 17 Apr 2025 14:41:55 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 3/4] PCI: Add link down handling for host bridges Content-Language: en-US To: Manivannan Sadhasivam Cc: Mahesh J Salgaonkar , Oliver O'Halloran , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , dingwei@marvell.com, cassel@kernel.org, Lukas Wunner , linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20250416-pcie-reset-slot-v2-0-efe76b278c10@linaro.org> <20250416-pcie-reset-slot-v2-3-efe76b278c10@linaro.org> <26b70e1b-861f-4c94-47a7-a267c41cadbb@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 8K31LvWb_wuIsiz-qtD9bR-p0tigEY48 X-Authority-Analysis: v=2.4 cv=JNc7s9Kb c=1 sm=1 tr=0 ts=6800c5e2 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=om0y8n2fdRonrlNA1WoA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 8K31LvWb_wuIsiz-qtD9bR-p0tigEY48 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-17_02,2025-04-15_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504170071 On 4/17/2025 1:24 PM, Manivannan Sadhasivam wrote: > On Wed, Apr 16, 2025 at 11:21:49PM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 4/16/2025 9:59 PM, Manivannan Sadhasivam via B4 Relay wrote: >>> From: Manivannan Sadhasivam >>> >>> The PCI link, when down, needs to be recovered to bring it back. But that >>> cannot be done in a generic way as link recovery procedure is specific to >>> host bridges. So add a new API pci_host_handle_link_down() that could be >>> called by the host bridge drivers when the link goes down. >>> >>> The API will iterate through all the slots and calls the pcie_do_recovery() >>> function with 'pci_channel_io_frozen' as the state. This will result in the >>> execution of the AER Fatal error handling code. Since the link down >>> recovery is pretty much the same as AER Fatal error handling, >>> pcie_do_recovery() helper is reused here. First the AER error_detected >>> callback will be triggered for the bridge and the downstream devices. Then, >>> pcie_do_slot_reset() will be called for each slots, which will reset the >>> slots using 'reset_slot' callback to recover the link. Once that's done, >>> resume message will be broadcasted to the bridge and the downstream devices >>> indicating successful link recovery. >>> >>> In case if the AER support is not enabled in the kernel, only >>> pci_bus_error_reset() will be called for each slots as there is no way we >>> could inform the drivers about link recovery. >>> >> The PCIe endpoint drivers are registering with err_handlers and they >> will be invoked only from pcie_do_recovery, but there are getting built >> by default irrespective of AER is enabled or not. >> > > AER is *one* of the functionalities of an endpoint. And the endpoint could > mostly work without AER reporting (except for AER fatal/non-fatal where recovery > need to be performed by the host). So it wouldn't make sense to add AER > dependency for them. > >> Does it make sense to built err.c irrespective of AER is enabled or not >> to use common logic without the need of having dependency on AER. >> > > Well, yes and no. Right now, only DPC reuses the err handlers except AER. But > DPC driver itself is functional dependent on AER. So I don't think it is really > required to build err.c independent of AER. But I will try to rework the code in > the future for fixing things like 'AER' prefix added to logs and such. > Right now we have DPC & AER to use this pcie_do_recovery(), now we are adding supporting for controller reported error (Link down) not sure if there will be newer ways to report errors in future. May be not in this series, in future better to de-couple err.c from AER as err.c. As the sources of error reporting is not limited to AER or DPC alone now. >> Also since err.c is tied with AER, DPC also had a hard requirement >> to enable AER which is not needed technically. >> > > DPC driver is functional dependent on AER. I got a impression by seeing below statement that DPC can work independently. As per spec 6 sec 6.2.11.2, DPC error signaling "A DPC-capable Downstream Port must support ERR_COR signaling, independent of whether it supports Advanced Error Reporting (AER) or not". In fact it can work if AER is not enabled also, but will not have full functionality of DPC. - Krishna Chaitanya. > > - Mani >